{"title":"动态偏置低功耗高性能3.3V输出缓冲器，单孔体CMOS 1.8V氧化物45nm工艺","authors":"K. Rajagopal","doi":"10.1109/ISQED.2012.6187489","DOIUrl":null,"url":null,"abstract":"Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process\",\"authors\":\"K. Rajagopal\",\"doi\":\"10.1109/ISQED.2012.6187489\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.\",\"PeriodicalId\":205874,\"journal\":{\"name\":\"Thirteenth International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"193 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Thirteenth International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2012.6187489\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2012.6187489","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.
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