Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第9页

A design-for-test apparatus for measuring on-chip temperature with fine granularity 一种用于测量细粒度片上温度的专为测试而设计的仪器

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187470

James S. Tandon, M. Sasaki, M. Ikeda, K. Asada

{"title":"A design-for-test apparatus for measuring on-chip temperature with fine granularity","authors":"James S. Tandon, M. Sasaki, M. Ikeda, K. Asada","doi":"10.1109/ISQED.2012.6187470","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187470","url":null,"abstract":"We present a design-for-test apparatus for measuring real-time, on-chip heat map images with high granularity. Our test chip implemented an 8 × 8 matrix of temperature sensors on-chip in a 0.18μm process with minimal area and power consumption overhead. We then implemented a test interface for measuring individual temperatures with an off-chip ADC and a custom FPGA-based microcontroller with serial UART and ethernet capabilities. This apparatus was used to animate the variation in temperature across the die over time. While temperature sensors have been integrated extensively in VLSI circuits, a single sensor cannot take accurate measurements across an entire chip. Infrared cameras are excellent for direct measurement of temperature across a die, however with new, so-called 3D integrated circuit technology, an infrared camera cannot measure the temperature inside a three dimensional stack. Since performance, reliability, and power consumption are all related to temperature, operating constraints for temperature must be verified to ensure proper device operation. Our design-for-test apparatus demonstrates that fine-grain, real-time measurements of temperature on-chip can be accomplished in real-time with less than 0.5% area overhead in a 1.5 × 1.5mm2 total core area, and less than 1mW power consumption added to the device under test (DUT).","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs 一维网格设计中贴装后光刻热点检测与去除

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187494

Jen-Yi Wuu, Mark Simmons, M. Marek-Sadowska

引用次数: 2

On lithography aware metal-fill insertion 在光刻上感应金属填充插入

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187495

Vikram B. Suresh, P. Vijayakumar, S. Kundu

{"title":"On lithography aware metal-fill insertion","authors":"Vikram B. Suresh, P. Vijayakumar, S. Kundu","doi":"10.1109/ISQED.2012.6187495","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187495","url":null,"abstract":"Manufacturability and lithographic printability are growing concerns with advancing technology nodes. The two most important parameters which influence the printability of a design are lithographic process corner and pattern density of the design. Dummy metal-fills are used to improve post-chemical mechanical polishing surface planarity. Conventional metal-fills do not consider impact of fill on lithographic printability or critical area-this is the focus of our paper. Although systematic yield due to lithographic distortions is gaining prominence, paniculate defects still remain a significant source of yield loss. Increasing design density in conjunction with growing manufacturability issues necessitates lithography aware paniculate limited yield loss analysis. In this work, we propose a novel lithography aware metal-fill insertion technique taking both statistical lithographic variations and critical area into consideration. Specifically, the main contributions of this work are a) analyzing the influence of metal-fills on line width variation and critical area, b) synthesis of variational lithography-aware metal-fill to improve design yield. The solution is been built on existing commercial tools. Experiments on ISCAS'85 benchmark circuits reveal that in 45nm technology, metal-fills worsen the linewidth variation by as much as 15% for more than 30% of nets compared to no fill. By contrast, proposed lithography aware metal-fill reduces linewidth variation by -25% and critical area by -35% compared to conventional metal-fill solutions without sacrificing density, planarity and performance targets.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131178227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An analytical approach to efficient circuit variability analysis in scaled CMOS design 一种有效的CMOS电路变异性分析方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187560

Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, C. Chakrabarti

引用次数: 20

A complete power estimation methodology for DSP blocks in FPGAs fpga中DSP模块的完整功率估计方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187502

Hassan Hassan, N. Abdallah

引用次数: 3

Algorithmic study on the routing reliability problem 路由可靠性问题的算法研究

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187537

Q. Ma, Zigang Xiao, Martin D. F. Wong

引用次数: 2

Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications 用于WiMax和MMDS应用的元模型辅助的超快速模因优化锁相环

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187552

Oleg Garitselov, S. Mohanty, E. Kougianos, Oghenekarho Okobiah

{"title":"Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications","authors":"Oleg Garitselov, S. Mohanty, E. Kougianos, Oghenekarho Okobiah","doi":"10.1109/ISQED.2012.6187552","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187552","url":null,"abstract":"With CMOS technologies progressing deeper into the nano-scale domain the design of analog and mixed-signal components is becoming very challenging. The presence of parasitics and the complexity of calculations involved create an enormous challenge for designers to keep their design within specifications when reaching the physical layout stage of the design process. This paper proposes a novel ultra-fast design flow that uses memetic-based optimization algorithms over neural-network based non-polynomial metamodels for design-space exploration. A new heuristic optimization algorithm which is based on memetic algorithms and artificial bee colony optimization is introduced. The design flow relies on a multiple-layer feedforward neural network metamodel of the nano-CMOS circuit. Using a CMOS PLL circuit it is shown that the proposed design flow is flexible and robust while it achieves optimal design to two different wireless specifications, WiMax and MMDS. Experimental results show that the proposed approach is 2.4 × faster than the swarm based optimization over the same metamodels.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122135940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic 基于延迟不敏感代码的定时和软错误弹性和自适应性能逻辑

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187475

Bao Liu, Xuemei Chen, F. Teshome

{"title":"Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic","authors":"Bao Liu, Xuemei Chen, F. Teshome","doi":"10.1109/ISQED.2012.6187475","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187475","url":null,"abstract":"Nanoscale VLSI systems are subject to increasingly prevalent catastrophic defects, soft errors, and significant parametric variations, which cannot be reduced below certain levels according to quantum physics, and must be handled by new design methods. In this paper, we leverage the existing fault-secure logic design techniques, and propose resilient and adaptive-performance (RAP) logic based on delay-insensitive (DI) code and inversion-free logic. RAP logic clears all timing errors and achieves adaptive maximum performance in the absence of external soft errors at a higher area/power cost compared with the existing logic paradigms. Our experimental results further demonstrate that dual-rail static (Domino) RAP logic outperforms alternative delay-insensitive (DI) code-based static (Domino) RAP logic with less area, higher performance and lower power consumption in all test cases, and achieves an average of 2.29(2.41)× performance boost, 2.12(1.91)× layout area and 2.38(2.34)× power consumption compared with the traditional minimum area static logic based on the Nangate 45nm open cell library.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127074720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physical-design-friendly hierarchical logic built-in self-test—A case study 物理设计友好的分层逻辑内置自检-一个案例研究

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187466

Kelvin Nelson, Jaga Shanmugavadivelu, J. Mekkoth, V. Ghanta, Jun Wu, Fei Zhuang, H. Chao, Shianling Wu, J. Rao, Lizhen Yu, Laung-Terng Wang

引用次数: 0

Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects 全球VLSI互连中MWNT和捆绑SWNT串扰延迟和面积分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187508

M. Majumder, Nisarg D. Pandya, B. Kaushik, S. Manhas

引用次数: 12