Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications

With CMOS technologies progressing deeper into the nano-scale domain the design of analog and mixed-signal components is becoming very challenging. The presence of parasitics and the complexity of calculations involved create an enormous challenge for designers to keep their design within specifications when reaching the physical layout stage of the design process. This paper proposes a novel ultra-fast design flow that uses memetic-based optimization algorithms over neural-network based non-polynomial metamodels for design-space exploration. A new heuristic optimization algorithm which is based on memetic algorithms and artificial bee colony optimization is introduced. The design flow relies on a multiple-layer feedforward neural network metamodel of the nano-CMOS circuit. Using a CMOS PLL circuit it is shown that the proposed design flow is flexible and robust while it achieves optimal design to two different wireless specifications, WiMax and MMDS. Experimental results show that the proposed approach is 2.4 × faster than the swarm based optimization over the same metamodels.