Speed-path analysis for multi-path failed latches with random variation

Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, H. Komatsu
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引用次数: 1

Abstract

In processor and high-end chip designs, path delay difference between pre-silicon and post-silicon have become an important issue. Identifying the factors for the difference with speed limiting paths is required to achieve target performance. A statistical diagnosis framework, called speed-path analysis, identifies them. Speed-path analysis uses fail data from at-speed delay test with silicon samples. Since at-speed delay test activates multiple paths simultaneously, it makes many failed latches with multiple sensitized paths. We will refer to these failed latches as multi-path failed latches. Previous works have not discussed how to handle multi-path failed latches because they are discussions under the assumption that path delay differences are obtained correctly. Generating additional test patterns to activate a single path for each latch is a very time-consuming task. Without using multi-path failed latches from at-speed delay test, the fatal factors for path delay differences with speed limiting paths can be missed because the number of non multi-path failed latches is small. This paper proposes methods for handling multi-path failed latches. By experiments based on a test processor design, we can deal with 12% of the timing-critical latches adopted as failed latches while 1% using only non multi-path failed latches.
随机变化多路径失效锁存器的速度路径分析
在处理器和高端芯片设计中,前置硅和后置硅之间的路径延迟差异已经成为一个重要的问题。为了实现目标性能,需要识别与限速路径差异的因素。一种称为速度路径分析的统计诊断框架可以识别它们。速度路径分析使用来自硅样品的高速延迟测试的故障数据。由于高速延迟测试同时激活了多个路径,导致多个敏化路径锁存失败。我们将这些失败的锁存称为多路径失败的锁存。以往的工作没有讨论如何处理多路径闩锁失效,因为它们是在正确获得路径延迟差的前提下进行讨论的。生成额外的测试模式来激活每个锁存器的单个路径是一项非常耗时的任务。由于非多路径闩锁失效的数量较少,不使用高速延迟测试的多路径闩锁失效,可以忽略与限速路径的路径延迟差异的致命因素。本文提出了处理多路径闩锁失效的方法。通过基于测试处理器设计的实验,我们可以处理12%的时间关键锁存器作为失效锁存器,而1%的时间关键锁存器仅使用非多路径失效锁存器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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