{"title":"Process variation tolerant 9T SRAM bitcell design","authors":"G. K. Reddy, K. Jainwal, Jawar Singh, S. Mohanty","doi":"10.1109/ISQED.2012.6187539","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187539","url":null,"abstract":"In this paper, a nine-transistor (9T) Static Random Access Memory (SRAM) bitcell for the low voltage and energy constraint applications is proposed. It is well known that in sub-threshold regime, reliability and process variations are the main design challenges, and standard six-transistor (6T) SRAM bitcell fails to operate in sub-VTH. The proposed design has better read stability and improved process variation tolerant as compared to standard 6T SRAM at low voltage. Simulation results based on 32nm technology node shows that there is 37% improvement in the read stability as compared to standard 6T SRAM bitcell. The proposed design also address the conflicting read and write requirements, therefore, one can optimize the read static noise margin (SNM), write noise margin and write speed for a particular application by selecting the bitcell ratios for read and write operations.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130326976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A case for 3D stacked analog circuits in high-speed sensing systems","authors":"Mohammad Abdel-Majeed, M. Chen, M. Annavaram","doi":"10.1109/ISQED.2012.6187526","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187526","url":null,"abstract":"In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116130657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masaharu Terada, S. Yoshimoto, S. Okumura, Toshikazu Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto
{"title":"A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction","authors":"Masaharu Terada, S. Yoshimoto, S. Okumura, Toshikazu Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ISQED.2012.6187538","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187538","url":null,"abstract":"This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125°C) and by 79% at a typical corner (CC, 25°C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132267577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. N. Tripathi, R. Nagpal, N. Chhabra, Rakesh Malik, J. Mukherjee
{"title":"Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization","authors":"J. N. Tripathi, R. Nagpal, N. Chhabra, Rakesh Malik, J. Mukherjee","doi":"10.1109/ISQED.2012.6187544","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187544","url":null,"abstract":"To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis","authors":"Keisuke Inoue, M. Kaneko","doi":"10.1109/ISQED.2012.6187579","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187579","url":null,"abstract":"Nowadays, clock skew becomes a manageable resource to improve circuits by assigning a certain clock delay to each register. However, it has been reported that implementing a large spectrum of dedicated clock delays becomes challenging in a reliable manner under several uncertainties. To overcome this limitation, multi-domain clock skew scheduling (MDCSS) has been proposed, and studied in logic- and physical-level design stages. This paper firstly introduce the concept of MDCSS into high-level synthesis, and shows that register binding and domain assignment have a significant impact on the performance of the resulting datapath. A mixed integer linear program model to optimize MDCSS-based datapath is presented, which can be used for various objectives in MDCSS-based design. Experiments on several benchmark circuits validate the effectiveness of the approach.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123992405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The combined effect of process variations and power supply noise on clock skew and jitter","authors":"Hu Xu, V. Pavlidis, W. Burleson, G. Micheli","doi":"10.1109/ISQED.2012.6187512","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187512","url":null,"abstract":"In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128711829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal via structural design in three-dimensional integrated circuits","authors":"L. Hwang, Kevin L. Lin, Martin D. F. Wong","doi":"10.1109/ISQED.2012.6187481","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187481","url":null,"abstract":"3D IC, a novel packaging technology, is heavily studied to realize improved performance with denser packaging and reduced wirelength. Despite numerous advantages, thermal management is the biggest bottleneck to realize device stacking technology. In this paper, we propose a thermal-aware physical design for three-dimensional integrated circuits (3D IC). We aim to mitigate localized hotspots to ensure functionality by adding thermal fin geometry to existing thermal through silicon via (TTSV). We analyze various ways to insert thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of a three-dimensional system is developed and a thermal resistance circuit is built for accurate and time-efficient 3D thermal analysis.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116309973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of variations in MOSFET versus CNFET in gigascale integrated systems","authors":"A. A. M. Shahi, P. Zarkesh-Ha, M. Elahi","doi":"10.1109/ISQED.2012.6187521","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187521","url":null,"abstract":"Using previously developed model for CNT density variation in CNFETs and random dopant fluctuation model in MOSFET, we compared and presented overall device variations in MOSFET and CNFET for gigascale integrated systems. Even if all of the sources of variation can be well-controlled in the manufacturing process, it is very hard (if not impractical) to control the dopant fluctuation in MOSFET and CNT density variation in CNFET device technology. Our analysis shows that in 32nm technology node, the random dopant fluctuation in a typical n-type MOSFET creates 1.1% on-current, 6.7% off-current, 0.23% input capacitance, and 1.6% threshold voltage variations, while the CNT density variation in a typical n-type CNFET with 10 CNTs in the channel creates 23% on-current, 22% off-current, 23% gate capacitance and only 0.011% threshold voltage variations. Based on our analysis, although the threshold voltage variation in CNFET is very small, the overall variations in CNFETs are worse than the variations in MOSFETs. As a result CNT density variation in CNFETs must be carefully taken into account for current gigascale and future terascale integrated systems.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117188140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning
{"title":"Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density","authors":"A. H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning","doi":"10.1109/ISQED.2012.6187493","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187493","url":null,"abstract":"Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10μm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. The extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6μm × 8μm, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114084277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis","authors":"Xin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang","doi":"10.1109/ISQED.2012.6187572","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187572","url":null,"abstract":"In this paper, an electro-thermal model is proposed for the first time to accurately investigate the self-heating effects in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) for thermal-aware design optimization. The model is derived based on the equivalent thermal network method, in which the impacts of gate length dependence, nanowire diameter dependence and surface roughness on the nanowire channel thermal conductivity as well as the influence of unique GAA structure features on the heat dissipation are taken into account. The proposed model agrees well with the experimental results of SNWTs. Based on the model, the impacts of structure parameters on the current driving capabilities and heat dissipation of SNWTs are discussed. The developed electro-thermal model can be further applied to the thermal-aware design of SNWT-based circuits.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123716872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}