Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

Process variation tolerant 9T SRAM bitcell design 过程变化容忍9T SRAM位元设计

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187539

G. K. Reddy, K. Jainwal, Jawar Singh, S. Mohanty

引用次数: 14

A case for 3D stacked analog circuits in high-speed sensing systems 高速传感系统中的三维堆叠模拟电路

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187526

Mohammad Abdel-Majeed, M. Chen, M. Annavaram

{"title":"A case for 3D stacked analog circuits in high-speed sensing systems","authors":"Mohammad Abdel-Majeed, M. Chen, M. Annavaram","doi":"10.1109/ISQED.2012.6187526","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187526","url":null,"abstract":"In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116130657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction 40nm 256kb 0.6 v操作半选择弹性8T SRAM，具有顺序写入技术，可实现367 mv VDDmin降低

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187538

Masaharu Terada, S. Yoshimoto, S. Okumura, Toshikazu Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

{"title":"A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction","authors":"Masaharu Terada, S. Yoshimoto, S. Okumura, Toshikazu Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ISQED.2012.6187538","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187538","url":null,"abstract":"This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125°C) and by 79% at a typical corner (CC, 25°C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132267577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization 利用粒子群优化算法抑制功率平面上腔模反共振峰以保持功率完整性

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187544

J. N. Tripathi, R. Nagpal, N. Chhabra, Rakesh Malik, J. Mukherjee

引用次数: 7

Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis 面向多域时钟倾斜调度的高级综合的寄存器绑定和域分配

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187579

Keisuke Inoue, M. Kaneko

引用次数: 0

The combined effect of process variations and power supply noise on clock skew and jitter 工艺变化和电源噪声对时钟偏差和抖动的综合影响

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187512

Hu Xu, V. Pavlidis, W. Burleson, G. Micheli

引用次数: 18

Thermal via structural design in three-dimensional integrated circuits 三维集成电路的热通结构设计

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187481

L. Hwang, Kevin L. Lin, Martin D. F. Wong

引用次数: 6

Comparison of variations in MOSFET versus CNFET in gigascale integrated systems 兆兆级集成系统中MOSFET与CNFET变化的比较

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187521

A. A. M. Shahi, P. Zarkesh-Ha, M. Elahi

{"title":"Comparison of variations in MOSFET versus CNFET in gigascale integrated systems","authors":"A. A. M. Shahi, P. Zarkesh-Ha, M. Elahi","doi":"10.1109/ISQED.2012.6187521","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187521","url":null,"abstract":"Using previously developed model for CNT density variation in CNFETs and random dopant fluctuation model in MOSFET, we compared and presented overall device variations in MOSFET and CNFET for gigascale integrated systems. Even if all of the sources of variation can be well-controlled in the manufacturing process, it is very hard (if not impractical) to control the dopant fluctuation in MOSFET and CNT density variation in CNFET device technology. Our analysis shows that in 32nm technology node, the random dopant fluctuation in a typical n-type MOSFET creates 1.1% on-current, 6.7% off-current, 0.23% input capacitance, and 1.6% threshold voltage variations, while the CNT density variation in a typical n-type CNFET with 10 CNTs in the channel creates 23% on-current, 22% off-current, 23% gate capacitance and only 0.011% threshold voltage variations. Based on our analysis, although the threshold voltage variation in CNFET is very small, the overall variations in CNFETs are worse than the variations in MOSFETs. As a result CNT density variation in CNFETs must be carefully taken into account for current gigascale and future terascale integrated systems.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117188140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density 测试结构、电路和提取方法，以确定STI和多晶硅图案密度的影响半径

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187493

A. H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning

{"title":"Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density","authors":"A. H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning","doi":"10.1109/ISQED.2012.6187493","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187493","url":null,"abstract":"Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10μm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. The extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6μm × 8μm, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114084277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis 栅极全硅纳米线mosfet的自热效应:建模与分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187572

Xin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang

引用次数: 7