Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第4页

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms 基于贪婪线程交换的MPSoC平台动态电源管理分析与评价

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187557

C. Ravishankar, S. Ananthanarayanan, S. Garg, A. Kennings

{"title":"Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms","authors":"C. Ravishankar, S. Ananthanarayanan, S. Garg, A. Kennings","doi":"10.1109/ISQED.2012.6187557","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187557","url":null,"abstract":"Thread migration (TM) is a recently proposed dynamic power management technique for heterogeneous multi-processor system-on-chip (MPSoC) platforms that eliminates the area and power overheads incurred by fine-grained dynamic voltage and frequency scaling (DVFS) based power management. In this paper, we take the first step towards formally analyzing and experimentally evaluating the use of power-aware TM for parallel data streaming applications on MPSoC platforms. From an analysis perspective, we characterize the optimal mapping of threads to cores and prove the convergence properties of a complexity effective greedy thread swapping based TM algorithm to the globally optimal solution. The proposed techniques are evaluated on a 9-core FPGA based MPSoC prototype equipped with fully-functional TM and DVFS support, and running a parallelized video encoding benchmark based on the Motion Picture Experts Group (MPEG-2) standard. Our experimental results validate the proposed theoretical analysis, and show that the proposed TM algorithm provides within 8% of the DVFS performance under the same power budget, and assuming no overheads for DVFS. Assuming voltage regulator inefficiency of 80%, the proposed TM algorithm has 9% higher performance than DVFS, again under the same total power budget.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Learning based DVFS for simultaneous temperature, performance and energy management 基于学习的DVFS，用于同时进行温度、性能和能量管理

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187575

Hao Shen, Jun Lu, Qinru Qiu

引用次数: 66

Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits 自旋扭矩装置的互连分析:性能建模，最佳中继器插入和电路尺寸限制

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187507

S. Rakheja, A. Naeemi

{"title":"Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits","authors":"S. Rakheja, A. Naeemi","doi":"10.1109/ISQED.2012.6187507","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187507","url":null,"abstract":"A spin-torque device may be considered as the basic building block of an information processing system utilizing electron spin as the state variable. In this paper, interconnection aspects of spin-torque circuits are analyzed and their performance and energy dissipation are compared against those of their conventional electrical counterparts at the 7.5nm technology node. Spin circuits with two flavors of nanomagnet dynamics are considered: (a) nanomagnets with complete spin-torque assisted switching and (b) nanomagnets with mixed-mode switching utilizing Bennett clocking. The interconnect in the spin-torque logic is assumed to be implemented with graphene nanoribbons. It is found that a spin system with a full spin-torque assisted switching may have energy dissipation equal to that of the CMOS system only if electrical currents as low as 250nA are utilized with half-metal ferromagnet electrodes. To account for the spin signal loss within the interconnect, spin repeaters must be inserted along the interconnect. It is found that the optimal repeater insertion frequency to minimize the delay of the spin system is 2-3× higher than the critical repeater insertion frequency (to compensate only for signal losses.) Using Rent's rule-based interconnect density function in a random logic block, a comparison of the average performance and energy dissipation of spin and CMOS circuits as a function of circuit size and complexity is provided. The upper bound on the size of the spin circuit in the presence of spin repeaters is also quantified.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An enhanced debug-aware network interface for Network-on-Chip 一个增强的调试感知网络接口，用于片上网络

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187569

Mohammad Hossein Neishaburi, Z. Zilic

{"title":"An enhanced debug-aware network interface for Network-on-Chip","authors":"Mohammad Hossein Neishaburi, Z. Zilic","doi":"10.1109/ISQED.2012.6187569","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187569","url":null,"abstract":"As emerging System on Chips (SoCs) tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming complex. The increase in complexity of IP blocks and on-chip communication has accentuated the need to enhance traditional debug methods for SoCs. In this paper, we propose a new debug aware Network Interface (NI). The proposed debug aware NI monitors the transactions issued by processing elements and extracts the global order of transactions from the local partial order of transactions. Moreover, the proposed interface provides a mechanism for a cross-triggers debugging. The modules in charge of cross-trigger debugging monitor the transactions issued by connected IP blocks and invoke appropriate debug operations at the right time. Trace data and trigger events are extracted and routed to Shared Direct Memory Access Unit (SDMAU). SDMAU combines debug traces from different NIs. The major benefits of using our proposed mechanism over traditional techniques are as follows: 1) the proposed debug aware NI can generate non-intrusively the global states of a system that involve multiple clock domains and enable validation of global properties, 2) It can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time, 3) SDMAU maintains an efficient transfer of trace data to an external memory and there is no need for a large internal trace memory.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131456813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Critical area driven dummy fill insertion to improve manufacturing yield 关键区域驱动假体填充，提高制造良率

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187514

Nishant Dhumane, S. Kundu

{"title":"Critical area driven dummy fill insertion to improve manufacturing yield","authors":"Nishant Dhumane, S. Kundu","doi":"10.1109/ISQED.2012.6187514","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187514","url":null,"abstract":"Non-planar surface may cause incorrect transfer of patterns during lithography. In today's IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Existing metal fill solutions target secondary goals minimizing timing and crosstalk impact. They may however reduce yield by increasing probability of failure (POF) due to particulate defects. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line spacing. In this work, we present a formulation to balance these competing goals and provide a comparative study of greedy (or fixed spacing), variable spacing and LP formulation based fill insertions based on scalability and quality of solution. Finally, we extend the critical area based solution to include SRAF insertion in order to account for optical diffraction in lithography. The key contributions of this paper are i) layout density analysis model, ii) heuristic greedy, variable spacing and LP formulation based fill insertion techniques and iii) characterization and implementation of inter-feature spacing based SRAF insertion. Thus the proposed solution addresses both lithography and particulate related defects. Experimental results based on layout of ISCAS 85 benchmark circuits show that the variable spacing and the LP formulation based fill insertion techniques result in substantially reduced critical area while satisfying the layout density and uniformity criteria.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116627985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip 芯片上混合光子网络合成的粒子群优化方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187477

Shirish Bahirat, S. Pasricha

引用次数: 21

Process mismatch analysis based on reduced-order models 基于降阶模型的工艺失配分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187561

M. B. Yelten, P. Franzon, M. Steer

{"title":"Process mismatch analysis based on reduced-order models","authors":"M. B. Yelten, P. Franzon, M. Steer","doi":"10.1109/ISQED.2012.6187561","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187561","url":null,"abstract":"This paper describes a methodology based on reduced-order models to investigate the effects of process mismatch in analog circuits in the presence of reliability degradation. Neural network-based reduced-order models for the DC drain current, Ids, of 65 nm n- and p-channel transistors have been generated in terms of six process parameters, temperature, and device age. The models identify the contribution of process parameters to the mismatch of n- and p-channel transistors as they age. Hot carrier injection (HCI) is considered as the main reliability degradation for n-channel devices and negative bias temperature instability (NBTI) is considered for p-channel devices. It is demonstrated that the variations of the effective channel length and intrinsic threshold voltage are major contributors to device mismatch in the absence of aging. Finally, a beta multiplier current reference is analyzed using the developed models for the impact of process mismatch with and without the aging effects. It is shown that in a cascode current mirror the variability of the reference current can be reduced by ensuring that the same rail transistors experience similar variations.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133126657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An extended-range incremental CT ∑Δ ADC with optimized digital filter 一种带优化数字滤波器的增程增量式CT∑Δ ADC

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187492

Julian Garcia, A. Rusu

引用次数: 3

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating 基于睡眠深度控制的多模电源门控节能技术

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187558

S. Takeda, Shinobu Miwa, K. Usami, Hiroshi Nakamura

{"title":"Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating","authors":"S. Takeda, Shinobu Miwa, K. Usami, Hiroshi Nakamura","doi":"10.1109/ISQED.2012.6187558","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187558","url":null,"abstract":"Power Gating (PG) and Body Biasing (BB) are effective schemes to save leakage power in standby-time. However, in run-time, their large overhead energy and latency for sleep control prevent the circuit from saving power in short idle times. To reduce those overheads, advanced PG and BB using shallow sleep mode are studied. Those circuits achieve leakage saving even in short idle time. The depth of sleep mode has trade-offs between the overheads and the amount of saved leakage power; hence, making decision of depth of a shallow sleep is an important issue to maximize total leakage saving. However, the depth which achieves best leakage saving depends heavily on run-time factors, such as application behavior and temperature. Thus, the conventional circuit has multiple shallow sleep modes and chooses an adequate mode in run-time. However, it causes large overhead power because of additional voltage generators for shallow sleep modes. In this paper, we propose a sleep control scheme named Opt-static for run-time leakage saving. Our scheme uses only one shallow sleep mode, but its depth is reconfigurable. It successfully achieves leakage saving by adopting its depth with run-time factors. In addition, our scheme needs only one active voltage generator; hence overhead power associated with voltage generators is smaller than the conventional circuit which has multiple shallow sleep modes. Experimental results show that our schemes applied to Multi-mode PG achieves higher leakage saving than the conventional Multi-mode PG which has two shallow sleep modes, although it does not take into account for overhead power of voltage generators.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Enhancing efficiency and robustness of a photovoltaic power system under partial shading 提高部分遮阳条件下光伏发电系统的效率和稳健性

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187554

Yanzhi Wang, X. Lin, Younghyun Kim, N. Chang, Massoud Pedram

{"title":"Enhancing efficiency and robustness of a photovoltaic power system under partial shading","authors":"Yanzhi Wang, X. Lin, Younghyun Kim, N. Chang, Massoud Pedram","doi":"10.1109/ISQED.2012.6187554","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187554","url":null,"abstract":"Photovoltaic (PV) power systems have been widely applied in commercial and domestic facilities. Electrical energy storage (EES) systems are mandatory in standalone PV systems for continuous power supply. In this paper the efficiency and robustness enhancement methods for PV systems under partial shading have been investigated. Partial shading due to moving clouds and shadows of nearby obstacles on a PV module array causes significant efficiency degradation, since shaded and non-shaded PV modules have large discrepancy in their maximum power points (MPPs). Use of Individual charger for each PV module may mitigate the negative effect from partial shading. However, this method alone may still face severe energy efficiency degradation caused by i) the energy loss due to parasitic effects in the EES elements under variable incoming power from the PV modules and ii) the energy loss in each charger incurred by potentially high imbalance between its input and output voltages. This paper proposes three methods to enhance the PV system efficiency and robustness under partial shading: i) incorporation of a HEES (hybrid electrical energy storage) system into the PV system, ii) extension of the MPTT (maximum power transfer tracking) approach, and iii) dynamic PV module reconfiguration. The three proposed methods can be effectively combined together, yielding a significant efficiency gain ranging from 17.1% to 53.3% compared with the baseline systems.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134441782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30