Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第5页

NoC-based platform for embedded software design: An extension of the Hellfire Framework 基于noc的嵌入式软件设计平台:地狱火框架的扩展

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187480

F. Magalhães, Oliver B. Longhi, S. J. Filho, A. Aguiar, Fabiano Hessel

引用次数: 2

Placement aware clock gate cloning and redistribution methodology 位置感知时钟门克隆和重新分配方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187529

Ramamurthy Vishweshwara, Nagabhiru Mahita, R. Venkatraman

引用次数: 2

Understanding, modeling, and detecting pooling hotspots in copper CMP 理解、建模和检测铜CMP中的池热点

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187496

A. Gower-Hall, Tamba Gbondo-Tugbawa, JenPin Weng, W. Tseng, L. Economikos, T. Yanagisawa, Pavan Bashaboina, S. Greco

{"title":"Understanding, modeling, and detecting pooling hotspots in copper CMP","authors":"A. Gower-Hall, Tamba Gbondo-Tugbawa, JenPin Weng, W. Tseng, L. Economikos, T. Yanagisawa, Pavan Bashaboina, S. Greco","doi":"10.1109/ISQED.2012.6187496","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187496","url":null,"abstract":"Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). These failures occur when the overburden copper and/or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines. We first sought to understand the source of this failure mode, based on recently reported research and data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. These models can be used to improve CMP process optimization and/or Design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123521895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits VDDmin限制超低电压逻辑电路中64个电压域的后期双电源电压控制使功耗降低24%

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187553

T. Yasufuku, K. Hirairi, Y. Pu, Y. Zheng, Ryo Takahashi, Masato Sasaki, H. Fuketa, A. Muramatsu, M. Nomura, H. Shinohara, M. Takamiya, T. Sakurai

{"title":"24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits","authors":"T. Yasufuku, K. Hirairi, Y. Pu, Y. Zheng, Ryo Takahashi, Masato Sasaki, H. Fuketa, A. Muramatsu, M. Nomura, H. Shinohara, M. Takamiya, T. Sakurai","doi":"10.1109/ISQED.2012.6187553","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187553","url":null,"abstract":"A post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (VDDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average VDD below VDDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC'S circuit fabricated in 65nm CMOS. The layout of DES CODEC'S is divided into 64 VDD domains and each domain size is 54μm × 63.2μm. High VDD (VDDH) or low VDD (VDDL) is applied to each domain and the selection of VDD's is performed based on multiple built-in self tests. VDDH is selected in VDDmin-critical domains, while VDDL is selected in VDDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, VDDH = 3D437mV, and VDDL = 3D397mV.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Methodology for analysis of TSV stress induced transistor variation and circuit performance TSV应力诱导晶体管变化和电路性能分析方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187497

Li Yu, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning

{"title":"Methodology for analysis of TSV stress induced transistor variation and circuit performance","authors":"Li Yu, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, D. Boning","doi":"10.1109/ISQED.2012.6187497","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187497","url":null,"abstract":"As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129546226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Power-Performance Yield optimization for MPSoCs using MILP 基于MILP的mpsoc功率性能良率优化

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187577

K. Bhardwaj, Sanghamitra Roy, Koushik Chakraborty

{"title":"Power-Performance Yield optimization for MPSoCs using MILP","authors":"K. Bhardwaj, Sanghamitra Roy, Koushik Chakraborty","doi":"10.1109/ISQED.2012.6187577","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187577","url":null,"abstract":"In nanometer technology regime, process variation (PV) causes uncertainties in the processor frequency and leakage power, affecting the overall performance and energy efficiency of Multi-Processor System-on-Chips (MPSoCs). Mostly, the Power and Performance Yield optimizations are not done simultaneously while scheduling the tasks at the system level. We demonstrate the significance of optimizing both Power and Performance Yields simultaneously in task scheduling in order to minimize the effects of process variation at the system level. In this paper, we present process variation aware task scheduling algorithms and define a new design metric, called Power-Performance Yield (PPY) to guide the scheduling procedure. The PPY is modeled considering the spatial correlation characteristic of systematic process variation, log-normal distributions of leakage power and an energy-aware slack budgeting approach. We propose a novel mathematical formulation using Mixed Integer Linear Programming (MILP) technique and also employ an improved Simulated Annealing (SA) based stochastic technique for PPY optimization. The experimental results on TGFF generated random task graphs and E3S benchmark suite demonstrate average PPY improvements of 16.9% and 31% over two other SA based schemes that separately optimize Performance Yield and Power Yield, respectively. With accurate PV-aware modeling, we obtain average PPY improvements of 9.65% and 30.3% under strong correlations and 12.9% and 29.8% under weak correlations when compared to two other existing scheduling schemes that lack appropriate modeling.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129728778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Theory of redundancy for logic circuits to maximize yield/area 使产量/面积最大化的逻辑电路冗余理论

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187563

M. Mirza-Aghatabar, M. Breuer, S. Gupta, Shahin Nazarian

{"title":"Theory of redundancy for logic circuits to maximize yield/area","authors":"M. Mirza-Aghatabar, M. Breuer, S. Gupta, Shahin Nazarian","doi":"10.1109/ISQED.2012.6187563","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187563","url":null,"abstract":"The down scaling of feature sizes and higher process variations in future CMOS nano-technologies are anticipated to introduce higher manufacturing anomalies. On the other hand designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. These phenomena significantly reduce the functional yield. Redundancy has been used for a long time in regular structures such as memory to tolerate defects; however, for typical irregular logic circuits this would be very challenging. In this paper we introduce a theory that justifies the necessity of using redundancy at sub-chip level of granularity to maximize yield/area (number of healthy dies) for future technologies with higher defect rates. In addition, redundancy at finer levels of granularity, aggravates the overheads of interconnect (steering logics, i.e., forks, joins and switches) such as yield, area, and testing overheads. These overheads limit the level of granularity for logic replication. Current yield estimators are generally pessimistic for interconnects because they do not take circuit and logic context into consideration, and/or they assume all defects are killer-defects, i.e., always result in unacceptable circuit behavior. In this paper we propose a CAD tool to compute the functional yield of the configurable and testable steering logics using (i) actual layout geometries, and (ii) factory data related to density and size of opens (missing metal), shorts (extra metal) and open vias. The experimental results show that our theory of redundancy considering the overheads of steering logics can improve the yield/area by 2.8 times for a real highly-defected circuit (OpenSparc T2 core).","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129896494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS HiSIM-RP:基于逆向分析的第一原理紧凑MOSFET模型及其在90nm和40nm CMOS变异性分析中的应用

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187548

H. Sakamoto, S. Kumashiro, S. Sato, N. Wakita, T. Mogami

{"title":"HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS","authors":"H. Sakamoto, S. Kumashiro, S. Sato, N. Wakita, T. Mogami","doi":"10.1109/ISQED.2012.6187548","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187548","url":null,"abstract":"As traditional compact MOSFET models have many unphysical fitting parameters, they cannot be used for electrical characteristics prediction with process condition change. Moreover, they cannot be used for physical variability extraction from electrical characteristics variation, either. Although TCAD has the same potential capability, they are too slow for circuit simulation. In this paper, a reverse-profiling based 1st principles compact MOSFET model HiSIM-RP developed from HiSIM2 [1] is presented. HiSIM-RP does not have any unphysical fitting parameters and has 1,000-10,000 times faster calculation speed than TCAD. Good predictability of HiSIM-RP has been demonstrated in the case of channel profile change of 90nm transistor. Moreover, 90nm and 40nm CMOS electrical characteristics variability has been analyzed by HiSIM-RP. It has been clarified that random dopant fluctuation and external source/drain series resistance variation are the primary contributors to random variation of electrical characteristics. As for the systematic variation of the electrical characteristics, it has been clarified that gate length, dopant non-uniformity and external source/drain series resistance variation are the primary contributors.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131705695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC 基于noc的MPSoC能耗最小化分区与动态映射评价

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187532

Eduardo Antunes, Matheus Soares, A. Aguiar, S. J. Filho, M. Sartori, Fabiano Hessel, C. Marcon

引用次数: 12

Improved path clustering for adaptive path-delay testing 改进的路径聚类自适应路径延迟测试

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187468

T. Chan, A. Kahng

引用次数: 1