Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第6页

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield 实时流应用到mpsoc的过程变化感知映射，以提高产量

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187472

D. Mirzoyan, B. Akesson, K. Goossens

{"title":"Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield","authors":"D. Mirzoyan, B. Akesson, K. Goossens","doi":"10.1109/ISQED.2012.6187472","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187472","url":null,"abstract":"As technology scales, the impact of process variation on the maximum supported frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications. The three main contributions of this paper are: 1) Using data flow graphs that are well-suited for modeling and analysis of real-time streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding. 2) We present two approaches for optimizing the yield. The approaches give different results at different costs. 3) We present exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of real applications, and are compared to the mapping methods that are unaware of hardware variation. Our results demonstrate yield improvements of up to 50% with an average of 31%, showing the effectiveness of our approaches.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123976259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Wearout-aware compiler-directed register assignment for embedded systems 嵌入式系统的损耗感知编译器定向寄存器赋值

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187471

Fahad Ahmed, M. Sabry, David Atienza Alonso, L. Milor

{"title":"Wearout-aware compiler-directed register assignment for embedded systems","authors":"Fahad Ahmed, M. Sabry, David Atienza Alonso, L. Milor","doi":"10.1109/ISQED.2012.6187471","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187471","url":null,"abstract":"Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis 基于连续均值移位法的重要抽样蒙特卡罗优化及其在SRAM动态稳定性分析中的应用

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187551

Takeshi Kida, Y. Tsukamoto, Y. Kihara

引用次数: 17

A novel robust signaling scheme for high-speed low-power communication over long wires 一种新的用于长线路高速低功耗通信的鲁棒信令方案

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187491

M. Dave, M. Baghini, D. Sharma

引用次数: 1

A 3D IC designs partitioning algorithm with power consideration 一种考虑功耗的三维集成电路分划算法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187486

Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, W. Cheng, Mely Chen Chi

引用次数: 12

An accurate current source model for CMOS based combinational logic cell 基于CMOS组合逻辑单元的精确电流源模型

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187549

B. Kaur, Sandeep Vundavalli, S. Manhas, S. Dasgupta, B. Anand

引用次数: 3

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance 工艺诱导机械应力感知多螺距优化提高电路性能

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187570

N. Alam, B. Anand, S. Dasgupta

引用次数: 9

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices 小通道面积器件上nbti诱导阈值电压偏移的统计观察

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187510

Takashi Sato, H. Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, H. Ochi

引用次数: 5

Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture CPU+GPU异构架构的高效电热协同分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187519

Huang Kun, Yang Xu, Guoxing Zhao, Zuying Luo

{"title":"Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture","authors":"Huang Kun, Yang Xu, Guoxing Zhao, Zuying Luo","doi":"10.1109/ISQED.2012.6187519","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187519","url":null,"abstract":"Since supply voltage and temperature (V&T) directly influence IC performance and reliability, electro-thermal (ET) analysis including power/ground (P/G) analysis and thermal analysis is very important in IC design. On the observation that temperature's influence on leakage current (ET coupling effect) and supply voltage's influence on power consumption, this work proposes a novel iteration-based ET co-analysis method that simultaneously solves V&T and then with them to refresh power consumption for the next round of V&T solving. Different from present methods that regard the P/G analysis and thermal analysis as independent processes without interaction, the ET co-analysis method takes their interaction into the consideration, which leads to more practical results. Since both P/G analysis and thermal analysis are very time-consuming, this work further employs multi-thread and GPU parallel computing techniques to speed up the ET co-analysis based on a parallel computing system of CPU+GPU heterogeneous architecture (PCS_CGHA). Experimental results show that compared with our method, present ET analysis methods will give too pessimistic or optimistic results W/O considering ET coupling effect. And our efficient method on PCS_CGHA provides 44 times speedup over the naive analysis method with no acceleration.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127395317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration 具有数字背景校准的超低电压数字控制低差稳压器

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187488

Yongtae Kim, Peng Li

{"title":"An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration","authors":"Yongtae Kim, Peng Li","doi":"10.1109/ISQED.2012.6187488","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187488","url":null,"abstract":"In this paper, we describe a novel ultra-low voltage digitally controlled low-dropout (LDO) voltage regulator offering digitally controllable dynamic voltage scaling (DVS) for near/sub-threshold applications. We eliminate the reference voltage in conventional LDOs and adopt the reference clock that enables the proposed LDO to be controlled digitally. The analog components are replaced by digital counterparts which are able to operate at near/sub-threshold regime. Additionally, a digital background calibration scheme is proposed to minimize the regulated voltage errors due to process, voltage, and temperature (PVL) variations. The proposed LDO has been designed in a 90-nm regular Vt CMOS process and the active area is 0.038-mm2. The LDO can regulate the output voltage from 260-mV to 440-mV, while the input supply voltage is from 380-mV to 500-mV. It delivers 3-mA load current at a 500-mV input and the quiescent current is 30.8-μA. The current and power efficiencies reach 99.0% and 87.1%, respectively. Furthermore, the regulated output voltage of the proposed LDO is tunable digitally in run-time with various step sizes.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127005728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17