Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献

{"title":"TDDB-based performance variation of combinational logic in deeply scaled CMOS technology","authors":"Haiqing Nan, Li Li, K. Choi","doi":"10.1109/ISQED.2012.6187513","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187513","url":null,"abstract":"As CMOS technology is scaled down, the gate oxide is scaling aggressively. The defects in the gate oxide form traps over time and results in gate oxide break down. Time-dependent dielectric breakdown (TDDB) is considered as one of the most important reasons of performance variation of CMOS devices. Soft break down events do not cause immediate failure of the CMOS device but will affect the performance of the circuit, especially for future CMOS applications which are more susceptible to soft break down events. However, the reasons for delay variation (increase or decrease) after TDDB are not clear for researchers. In this paper, detail analysis and simulation results for the delay variation of digital circuit due to TDDB are demonstrated for different locations and levels using 32 nm CMOS technology. In this paper, we show that the circuit delay can be increased or decreased depending on the input rising or falling transition of the circuit as well as the number of consecutive gates which are affected by TDDB.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132536726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs","authors":"Kan Wang, Sheqin Dong, Yuchun Ma, S. Goto, J. Cong","doi":"10.1109/ISQED.2012.6187485","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187485","url":null,"abstract":"3D IC has become an attractive technology as it decreases interconnection distance and improves performance. However, it is faced with heat dissipation and temperature problem seriously. The high temperature will increase the interconnection delay, and lead to degradation of performance. Through-silicon-via (TSV) has been shown as an effective way to optimize heat distribution. However, the distribution of TSVs will potentially influence the interconnection delay. In this paper, we propose a performance-driven 3D TSV-planning (3D-PTSP) algorithm, which can generate good TSV distribution, to improve temperature. The thermal effects on critical path delay are analyzed with leakage power-temperature-delay dependence considered. A priority based TSV redistribution algorithm and network flow based signal via allocation algorithm help to improve both TSV number and critical path delay without increasing temperature. Experimental results show that the proposed method can improve total via number by 8.9% and reduce critical path delay by 15.8%.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133845489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic range estimation for systems with control-flow structures","authors":"Bin Wu","doi":"10.1109/ISQED.2012.6187520","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187520","url":null,"abstract":"It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore the overall circuit area, delay and power consumption. Many analytical approaches are proposed for dynamic range estimation. However, because of the intractable nature of control-flow structures, all currently available methods consider only the systems consisting of pure dataflow structures/operations, while the general digital applications always contain some control-flow structures, such as conditional branches and loops, that depend on the randomness of inputs or other variables. Failing to handle general control-flow structures seriously restricts the applicability of analytical methods for dynamic range estimation, and makes lack-of-insight and costly profiling the only solutions for many applications. In this paper, we propose the first analytical method capable of handling general control-flow structures (especially random branches and loops) by utilizing a powerful mathematic tool, polynomial chaos expansion (PCE). Our method brings the application scope of analytical method for range estimation to general systems with control-flow structures for the first time, and it achieves high accuracy and orders of magnitude more efficiency than profiling.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130521063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A design tradeoff study with monolithic 3D integration","authors":"Chang Liu, S. Lim","doi":"10.1109/ISQED.2012.6187545","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187545","url":null,"abstract":"This paper studies various design tradeoffs existing in the monolithic 3D integration technology. Different design styles in monolithic 3D ICs are studied, including transistor-level monolithic integration (MI-TR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115330522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation","authors":"Kareem Ragab, R. Gharpurey, M. Orshansky","doi":"10.1109/ISQED.2012.6187487","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187487","url":null,"abstract":"A novel digital calibration technique based on component redundancy and random diversity (CRRD) is used to enable robust high-gain positive-feedback (PF) amplifiers. Gain enhancement is achieved through output conductance cancellation which requires accurate calibration across process, voltage, and temperature. CRRD employs a set of redundant elements intentionally exhibiting high local variability, and the subset of the elements that best cancels amplifier's output conductance is employed. We develop a novel design methodology to rigorously predict: (1) how to partition the full configuration range between a fixed load and a tunable load, and (2) how, for a given partition, to size the tunable load elements. We prove that having a sizable coarse load is essential for reaching optimality. We apply the developed theory to the design of a 0.18μm CMOS test-chip implementing a 6×10 array of high-gain PF amplifiers based on CRRD. We demonstrate that the use of CRRD allows only linear increase of the array size, and its associated capacitance, with dB gain improvement, in contrast to exponential increase in earlier designs. Gains of ninety amplifiers from three different dies were measured and exceeded 64dB for 95% of the samples, up from an intrinsic gain of 28.5dB. A gain-bandwidth product of 186MHz was measured while consuming 65μA from a 1.8V supply.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single fault reliability analysis in FPGA implemented circuits","authors":"H. Jahanirad, K. Mohammadi, Pejman Attarsharghi","doi":"10.1109/ISQED.2012.6187473","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187473","url":null,"abstract":"Reliability analysis in FPGA implementation of logic circuits is an important issue in designing fault tolerant systems for faulty environments. In this paper an analytical method is developed for analyzing such systems. This method is based on signal probability propagation of faults from the location of appearance to final outputs of circuit. Single fault model is used for the faults occurred in routes and LUTs. In addition reconvergent fan-outs are handled using 16 correlation coefficients propagation approach. Experimental results show a good agreement between this method and Monte Carlo method for reliability analysis of MCNC benchmarks.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123592166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TSV and DFT cost aware circuit partitioning for 3D-SOCs","authors":"Amit Kumar, S. Reddy, I. Pomeranz, B. Becker","doi":"10.1109/ISQED.2012.6187469","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187469","url":null,"abstract":"3D-SOC technology has significant performance and power gains over 2D as interconnects can be shortened significantly. To accrue full benefits of reduced interconnect lengths large designs need to be partitioned into several dies. In this work we propose a hypergraph based multi-objective circuit partitioning scheme for 3D-SOCs that simultaneously reduces the number of inter die connections, which use through silicon vias (TSVs), and reduces additional DFT logic needed for pre-bond test of dies. An Ordered Block hypergraph partitioning scheme is proposed to achieve these objectives. Experimental results on several industrial circuits demonstrate the effectiveness of the proposed approach.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128527857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A top-down design methodology using virtual platforms for concept development","authors":"Mohit Shah, Brian Mears, C. Chakrabarti, A. Spanias","doi":"10.1109/ISQED.2012.6187531","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187531","url":null,"abstract":"Virtual platforms are widely used for system-level modeling, design and simulation. In this paper, we propose a virtual platform-based, top-down, system-level design methodology for developing and testing hardware/software right from the concept level and even before the architecture is finalized. The methodology is based on using tools such as QEMU, SystemC and TLM2.0 that starts with a functional, high-level description of the system and gradually refines the intricate architectural details. We present our results by testing a novel concept aimed at performing audio blogging. The system under consideration involves the design of a low-power wearable audio recorder, an Android application for user interface and a server for audio analysis. A virtual system consisting of three instances of QEMU and other tools was created to demonstrate the concept and to test this approach. Finally, we describe a suite of tools useful for quickly validating concepts and creating virtual platforms for early hardware/software codesign.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124692563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators","authors":"T. Chan, Puneet Gupta, A. Kahng, Liangzhen Lai","doi":"10.1109/ISQED.2012.6187559","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187559","url":null,"abstract":"As CMOS technology scales, circuit performance becomes more sensitive to manufacturing and environmental variations. Hence, there is a need to measure or monitor circuit performance during manufacturing and at runtime. Since each circuit may have different sensitivities to process variations, previous works have focused on synthesis of circuit performance monitors that are specific to a given design. In this work, we study the potential benefit of having multiple design-dependent monitors. We develop a systematic approach to the synthesis of multiple design-dependent monitors, as well as a corresponding delay estimation method. Our approach synthesizes design-dependent ring oscillators (DDROs) using standard library gates. This has the advantage of quick design turnaround time and reduced schedule impact, because the DDRO implementation can leverage automation in conventional implementation flows. Our delay estimation method seeks to minimize the number of parameters as well as computing resources (i.e., to limit information storage and exchange) used in delay estimation based on monitoring results. Experiments show that our delay estimation method using multiple DDROs reduces overestimation (timing margin) by up to 25% compared to use of a single DDRO.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129758584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations","authors":"S. Rakheja, Vachan Kumar","doi":"10.1109/ISQED.2012.6187573","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187573","url":null,"abstract":"With continued shrinking of device dimensions on chip, major advancements in intra chip interconnect technology are required to minimize delay, energy dissipation and cross-talk. In this paper, two alternative on-chip interconnect technology options are studied, namely the plasmonic and optical interconnects. It is shown that plasmonic interconnects can be 3 orders of magnitude faster than minimum sized CMOS interconnects at the 2016 technology node. However, their propagation length is limited to few microns and hence they can be used only as short local interconnects. Energy per bit of plasmonic interconnects is shot-noise limited and it increases exponentially with interconnect length. Cross-over length beyond which plasmonic interconnects become less energy efficient compared to CMOS interconnects is calculated. It is found to be 10 μm for Ag cylindrical plasmonic waveguides of 100-nm diameter embedded in SiO2 dielectric at free-space wavelength of 1μm. Although plasmonic interconnects show potential as future local interconnects, plasmonic switches are needed for their implementation at the GSI(GigaScale Integration) level. Without plasmonic switches the energy and circuit overhead associated with signal conversion will be prohibitive. Optical interconnects, on the other hand, are limited to be used only at the global level due to the fundamental limitations on their size. Although the native interconnect delay of optical interconnects is quite less, their bandwidth density is limited due to the fundamental limitations on the minimum pitch. Wavelength division multiplexing is identified as one of the solutions towards increasing the bandwidth density of optical interconnects. Critical length beyond which optical interconnects offer higher bandwidth compared to copper interconnects is identified to be equal to the chip edge in absence of WDM. In presence of 4 channel WDM, the critical length improves to 0.4cm. Critical length assessment based on energy comparison with CMOS interconnect is evaluated to be 0.15cm.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}