Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations

With continued shrinking of device dimensions on chip, major advancements in intra chip interconnect technology are required to minimize delay, energy dissipation and cross-talk. In this paper, two alternative on-chip interconnect technology options are studied, namely the plasmonic and optical interconnects. It is shown that plasmonic interconnects can be 3 orders of magnitude faster than minimum sized CMOS interconnects at the 2016 technology node. However, their propagation length is limited to few microns and hence they can be used only as short local interconnects. Energy per bit of plasmonic interconnects is shot-noise limited and it increases exponentially with interconnect length. Cross-over length beyond which plasmonic interconnects become less energy efficient compared to CMOS interconnects is calculated. It is found to be 10 μm for Ag cylindrical plasmonic waveguides of 100-nm diameter embedded in SiO2 dielectric at free-space wavelength of 1μm. Although plasmonic interconnects show potential as future local interconnects, plasmonic switches are needed for their implementation at the GSI(GigaScale Integration) level. Without plasmonic switches the energy and circuit overhead associated with signal conversion will be prohibitive. Optical interconnects, on the other hand, are limited to be used only at the global level due to the fundamental limitations on their size. Although the native interconnect delay of optical interconnects is quite less, their bandwidth density is limited due to the fundamental limitations on the minimum pitch. Wavelength division multiplexing is identified as one of the solutions towards increasing the bandwidth density of optical interconnects. Critical length beyond which optical interconnects offer higher bandwidth compared to copper interconnects is identified to be equal to the chip edge in absence of WDM. In presence of 4 channel WDM, the critical length improves to 0.4cm. Critical length assessment based on energy comparison with CMOS interconnect is evaluated to be 0.15cm.