Single fault reliability analysis in FPGA implemented circuits

Reliability analysis in FPGA implementation of logic circuits is an important issue in designing fault tolerant systems for faulty environments. In this paper an analytical method is developed for analyzing such systems. This method is based on signal probability propagation of faults from the location of appearance to final outputs of circuit. Single fault model is used for the faults occurred in routes and LUTs. In addition reconvergent fan-outs are handled using 16 correlation coefficients propagation approach. Experimental results show a good agreement between this method and Monte Carlo method for reliability analysis of MCNC benchmarks.