A novel robust signaling scheme for high-speed low-power communication over long wires

This paper describes a new capacitively coupled driver and a receiver with a new analog equalizer for high-speed low-power communication over long on-chip wires. The proposed signaling scheme improves upon state of the art capacitively driven interconnect based scheme for enhanced robustness and energy efficiency of the signaling scheme. The proposed signaling scheme has been designed in 90nm CMOS process. Simulations indicate that the proposed scheme can transmit and receive data at the rate of 3.22Gbps over a 10mm long channel while consuming only 0.107pJ/bit. This is the lowest reported energy/bit for high-speed on-chip communication over long on-chip wires. Monte Carlo and process corner simulations show that the proposed scheme allows up to 3Gbps of data rate even in the presence of intra-die and inter-die process variations.