Optimal microarchitectural design configuration selection for processor hard-error reliability

Abstract

Traditional design space exploration mainly focuses on performance and power consumption. However, as one of the first-class constraints for modern processor design, the relationship between hard-error reliability and processor configurations has not been well studied. In this paper, we investigate this relationship by exploring a large processor design space. We employ a rule search strategy, i.e. Patient Rule Induction Method, to generate a set of rules which choose optimal configurations for processor hard-error reliability and its tradeoff with performance and power consumption.