Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application

Y. Tsukamoto, M. Yabuuchi, H. Fujiwara, K. Nii, C. Shin, T. Liu
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Abstract

Quasi-Planar Tri-gate (QPT) Bulk MOSFETs are fabricated simply by slightly recessing the shallow trench isolation (STI) oxide prior to gate-stack formation. In this cost-effective manner, 7% higher performance with lower leakage current in QPT bulk devices (vs. planar bulk devices) is achieved. QPT-based single-port SRAM characteristics can be improved by employing circuit design techniques (i.e., read- and write-assist circuitry) to compensate for unequal improvements in n-channel vs. p-channel QPT devices, to improve cell yield.
用于单端口SRAM的准平面三栅极(QPT)体CMOS技术
准平面三栅极(QPT)体mosfet是通过在栅极堆形成之前稍微嵌入浅沟槽隔离(STI)氧化物来制造的。在这种具有成本效益的方式下,QPT体块器件(与平面体块器件相比)的泄漏电流较低,性能提高7%。基于QPT的单端口SRAM特性可以通过采用电路设计技术(即读写辅助电路)来改善,以补偿n通道与p通道QPT器件的不平等改进,从而提高细胞产量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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