Proceedings最新文献_第6页

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0459

Melanie Cajita, Renald Dechino, Marionne Javien, Nico Deus Villafranca

{"title":"Finite Element Analysis (FEA) and Fractography : Complementary Methods in Understanding the Factors Resulting to Hairline Die Crack on Chip-On-Lead (COL) Devices","authors":"Melanie Cajita, Renald Dechino, Marionne Javien, Nico Deus Villafranca","doi":"10.31399/asm.cp.istfa2023p0459","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0459","url":null,"abstract":"Abstract Several failures in Chip-On-Lead (COL) package from the customer were returned for Failure Analysis (FA). Containment activities were able to find similar failures. The connectivity of the silicon die to the leads uses gold wire. The die is in live bug position with respect to the package and is being held in place using non-conductive die attach epoxy. The identification of the Failure Mechanism (FMECH) utilized analysis flow involving non-destructive and destructive FA techniques. A hairline crack was found on the die between the two (2) corner pins. Based on lot history reviews, hairline die crack had a very low detectability at electrical test. Further collaboration with the process owners showed the need to identify the crack initiation, propagation and the factors that could result to this FMECH. Analysis of fracture or fractography was utilized in identifying the crack initiation point and propagation. Due to low detectability, identifying the factors resulting to die crack would require several evaluations and process mappings. Finite element analysis (FEA) was utilized to create models and simulation to identify factors that would result to highly stressed area identified through fractography. These additional data for the hairline crack were vital on the identification of root cause and formulation of corrective/preventive actions.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FIB-SEM Tomography Acquisition and Data Processing Optimization for Logic and Memory Structures FIB-SEM断层扫描采集和数据处理优化的逻辑和存储结构

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0387

Heiko Stegmann, Alexandre Laquerre

引用次数: 0

Metrologies to Monitor Contamination Fallout in the Cleanroom 监测洁净室污染沉降物的计量方法

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023tpu1

Victor K.F. Chia

引用次数: 0

LLE: Mitigating IC Piracy and Reverse Engineering by Last Level Edit LLE:通过最后的关卡编辑来减少IC盗版和逆向工程

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0360

Sazadur Rahman, Nitin Varshney, Farimah Farahmandi, Navid Asadi Zanjani, Mark Tehranipoor

{"title":"LLE: Mitigating IC Piracy and Reverse Engineering by Last Level Edit","authors":"Sazadur Rahman, Nitin Varshney, Farimah Farahmandi, Navid Asadi Zanjani, Mark Tehranipoor","doi":"10.31399/asm.cp.istfa2023p0360","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0360","url":null,"abstract":"Abstract Hardware obfuscation is a proactive design-for- trust technique against integrated circuit (IC) supply chain threats, i.e., intellectual property (IP) piracy and overproduction. Many studies have evaluated numerous obfuscation techniques, broadly classified as IC camouflaging, logic locking, and split manufacturing. In split manufacturing, threats introduced by an untrusted foundry are eliminated by manufacturing only the front-end of line (FEOL) layers in the high-end untrusted foundry, and back-end of line (BEOL) layers in the design house’s trusted low-end foundry to hide BEOL connections from the untrusted foundry. However, researchers proposed several attacks based on physical layout design heuristic, network-flow model, and placement-routing proximity to extract missing back-end of line connections. Nevertheless, split manufacturing suffers from yield due to challenges in properly aligning FEOL connections with the BEOL. This paper proposes LLE, which protects ICs from piracy and reverse-engineering by untrusted foundries. In this approach, we perform layout-level obfuscation by creating an intermediate metal layer mesh to obscure the BEOL connections from the FEOL. After fabrication from an untrusted foundry, the mesh can be edited using a focused-ion beam (FIB) editing tool in a trusted facility (e.g., FIB lab) to realize the actual inter- connection. Hence, unlike split manufacturing, LLE eliminates the requirement of a separate trusted foundry and establishes trust in the microelectronic supply chain by lowering cost and yield loss. To validate the effectiveness of LLE, we fabricated a test chip in MITLL Low- Power FDSOI CMOS Process. In the silicon test chip, we demonstrate that LLE can prevent IC piracy and reverse engineering with low costs and yield losses in the semiconductor supply chain.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Photon Emission Intensity Analysis for Leakage Source Identification 泄漏源识别中的光子发射强度分析

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0151

Zhigang Song, Franco Stellari, Phong Tran

{"title":"Photon Emission Intensity Analysis for Leakage Source Identification","authors":"Zhigang Song, Franco Stellari, Phong Tran","doi":"10.31399/asm.cp.istfa2023p0151","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0151","url":null,"abstract":"Abstract Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 25","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Fault Isolation of Stuck at Reset Hard Failures 复位时硬盘故障的电气故障隔离

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0054

Amrutha Sampath, Carey Wu, Kristofor Dickson

{"title":"Electrical Fault Isolation of Stuck at Reset Hard Failures","authors":"Amrutha Sampath, Carey Wu, Kristofor Dickson","doi":"10.31399/asm.cp.istfa2023p0054","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0054","url":null,"abstract":"Abstract Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Backside Analysis Strategy to Identify a Package Related Failure Mode at an Automotive Magnetic Sensor Device 汽车磁传感器器件封装相关失效模式的背面分析策略

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0109

M. Simon-Najasek, F. Naumann, S. Huebner, M. Lejoyeux, F. Altmann, A. Lindner

{"title":"Backside Analysis Strategy to Identify a Package Related Failure Mode at an Automotive Magnetic Sensor Device","authors":"M. Simon-Najasek, F. Naumann, S. Huebner, M. Lejoyeux, F. Altmann, A. Lindner","doi":"10.31399/asm.cp.istfa2023p0109","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0109","url":null,"abstract":"Abstract This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Event Capture with an Electron Beam Probing System 电子束探测系统的电事件捕获

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0164

Neel Leslie, James Vickers, Jennifer J Huening, Xianghong Tom Tong, Patrick Pardy

引用次数: 0

Fan Out for Advanced Packaging Applications 扇出先进的包装应用

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023tpa2

Jan Vardaman, John Hunt

引用次数: 0