LLE: Mitigating IC Piracy and Reverse Engineering by Last Level Edit

Sazadur Rahman, Nitin Varshney, Farimah Farahmandi, Navid Asadi Zanjani, Mark Tehranipoor
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Abstract

Abstract Hardware obfuscation is a proactive design-for- trust technique against integrated circuit (IC) supply chain threats, i.e., intellectual property (IP) piracy and overproduction. Many studies have evaluated numerous obfuscation techniques, broadly classified as IC camouflaging, logic locking, and split manufacturing. In split manufacturing, threats introduced by an untrusted foundry are eliminated by manufacturing only the front-end of line (FEOL) layers in the high-end untrusted foundry, and back-end of line (BEOL) layers in the design house’s trusted low-end foundry to hide BEOL connections from the untrusted foundry. However, researchers proposed several attacks based on physical layout design heuristic, network-flow model, and placement-routing proximity to extract missing back-end of line connections. Nevertheless, split manufacturing suffers from yield due to challenges in properly aligning FEOL connections with the BEOL. This paper proposes LLE, which protects ICs from piracy and reverse-engineering by untrusted foundries. In this approach, we perform layout-level obfuscation by creating an intermediate metal layer mesh to obscure the BEOL connections from the FEOL. After fabrication from an untrusted foundry, the mesh can be edited using a focused-ion beam (FIB) editing tool in a trusted facility (e.g., FIB lab) to realize the actual inter- connection. Hence, unlike split manufacturing, LLE eliminates the requirement of a separate trusted foundry and establishes trust in the microelectronic supply chain by lowering cost and yield loss. To validate the effectiveness of LLE, we fabricated a test chip in MITLL Low- Power FDSOI CMOS Process. In the silicon test chip, we demonstrate that LLE can prevent IC piracy and reverse engineering with low costs and yield losses in the semiconductor supply chain.
LLE:通过最后的关卡编辑来减少IC盗版和逆向工程
硬件混淆是一种针对集成电路(IC)供应链威胁(即知识产权(IP)盗版和生产过剩)的主动设计信任技术。许多研究已经评估了许多混淆技术,大致分为IC伪装,逻辑锁定和分裂制造。在分离制造中,不可信代工厂带来的威胁可以通过只在高端不可信代工厂制造生产线前端(FEOL)层,在设计公司的可信低端代工厂制造生产线后端(BEOL)层来消除,从而对不可信代工厂隐藏BEOL连接。然而,研究人员提出了几种基于物理布局设计启发式、网络流模型和位置路由接近的攻击来提取缺失的后端线路连接。然而,由于在正确对齐FEOL与BEOL连接方面存在挑战,拆分制造受到良率的影响。本文提出了LLE,它可以保护ic免受不可信代工厂的盗版和逆向工程。在这种方法中,我们通过创建一个中间金属层网格来模糊BEOL与FEOL的连接,从而执行布局级混淆。在不可信的铸造厂制造后,可以在可信的设施(例如FIB实验室)中使用聚焦离子束(FIB)编辑工具编辑网格,以实现实际的互连。因此,与分裂制造不同,LLE消除了对独立可信代工厂的要求,并通过降低成本和产量损失在微电子供应链中建立信任。为了验证LLE的有效性,我们在MITLL低功耗FDSOI CMOS工艺中制作了一个测试芯片。在硅测试芯片中,我们证明了LLE可以在半导体供应链中以低成本和产量损失防止IC盗版和逆向工程。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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