{"title":"Electrical Fault Isolation of Stuck at Reset Hard Failures","authors":"Amrutha Sampath, Carey Wu, Kristofor Dickson","doi":"10.31399/asm.cp.istfa2023p0054","DOIUrl":null,"url":null,"abstract":"Abstract Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2023p0054","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Abstract Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.