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2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)最新文献

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Edge effect under temperature bias stress of 0.18 /spl mu/m PMOS technology 0.18 /spl mu/m PMOS技术温度偏置应力下的边缘效应
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314911
D. Chandra Sekhar, P. Pratim Ray, M. M. De Souza, P. Chaparala
{"title":"Edge effect under temperature bias stress of 0.18 /spl mu/m PMOS technology","authors":"D. Chandra Sekhar, P. Pratim Ray, M. M. De Souza, P. Chaparala","doi":"10.1109/ICMEL.2004.1314911","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314911","url":null,"abstract":"Edge effects under positive and negative bias temperature stress (PBTI and NBTI) of 0.18 /spl mu/m PMOS technology are quantified in terms of the parasitic source-drain series resistance. For the first time it is demonstrated that the series resistance degradation under NBTI is channel length independent although the shift in absolute parameter change increases with reducing channel length. Under NBTI the threshold voltage shifts towards more negative values. The damage mechanism is predominantly by donor type interface states, with a minor contribution of bulk traps. Under PBTI, damage in the centre of the channel, attributed to electron traps causes a shift in threshold voltage towards more positive values, whereas donor type interface states generated towards the edge of the channel contribute to a minor increase in series resistance. PBTI causes lesser damage in comparison to NBTI.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"6 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123649633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fully paramaterisable Galois Field arithmetic processor over GF(3/sup m/) suitable for elliptic curve cryptography 适用于椭圆曲线密码的GF(3/sup m/)上的全参数伽罗瓦域算术处理器
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314938
T. Kerins, E. Popovici, W. Marnane
{"title":"Fully paramaterisable Galois Field arithmetic processor over GF(3/sup m/) suitable for elliptic curve cryptography","authors":"T. Kerins, E. Popovici, W. Marnane","doi":"10.1109/ICMEL.2004.1314938","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314938","url":null,"abstract":"In this paper we present an architecture for a flexible GF(3/sup m/) multiplicative arithmetic processor. The ABC processor performs computations of the form R = (AB/C) mod F in 27n clock cycles, where A,B,C and F are polynomials over GF(3). The same hardware can be used for different field sizes offering full paramaterisability up to a maximum field size. We present prototype implementation results on FPGA for a field size of GF(3/sup 255/). The processor is suitable for cryptographic applications where variable levels of security are required.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Future memory technology including emerging new memories 未来存储器技术，包括新兴存储器
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314646
K. Kim, G. Koh
{"title":"Future memory technology including emerging new memories","authors":"K. Kim, G. Koh","doi":"10.1109/ICMEL.2004.1314646","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314646","url":null,"abstract":"There have been concerns about how far we can extend the so far so successful conventional semiconductor memories Such as DRAM, SRAM and Flash memory and what will be the future directions of memory development. In this article, we will review the key technical limits of conventional memory scaling and the directions to overcome the problem. In addition, we will review the technical challenges and opportunities of emerging. new memories such as ferroelectric RAM (FRAM), magnetic RAM (MRAM) and phase change RAM (PRAM) which has been recently focused as candidates for ideal memory which can solve the problems of conventional memories.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125886399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Three-dimensional topography simulation for deposition and etching processes using a level set method 用水平集方法模拟沉积和蚀刻过程的三维地形
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314606
A. Sheikholeslami, C. Heitzinger, T. Grasser, S. Selberherr
{"title":"Three-dimensional topography simulation for deposition and etching processes using a level set method","authors":"A. Sheikholeslami, C. Heitzinger, T. Grasser, S. Selberherr","doi":"10.1109/ICMEL.2004.1314606","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314606","url":null,"abstract":"We present, the application of level set and fast marching methods to the simulation of surface topography of a wafer in three dimensions for deposition and etching processes. These simulations rest on many techniques, including a narrow band level set method, fast marching for the Eikonal equation, extension of the speed function, transport models, visibility determination, and an iterative equation solver.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent developments in SiC power devices and related technology 碳化硅功率器件及相关技术的最新进展
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314551
J. Millán, P. Godignon, D. Tournier
{"title":"Recent developments in SiC power devices and related technology","authors":"J. Millán, P. Godignon, D. Tournier","doi":"10.1109/ICMEL.2004.1314551","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314551","url":null,"abstract":"This paper is an overview of recent progress in the development of high-voltage SiC power devices. Main issues on materials and SiC related process technology are also discussed. A detailed review of current situation and trends in SiC power rectifiers and switches is also given. Finally, an application of the SiC JFETs as a current limiter device is reported, showing the viability of SiC devices in certain applications.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The influence of bulk parameters on the switching behavior of FWDs for traction application 体积参数对牵引用fwd切换行为的影响
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314577
H. Felsl, E. Falck, M. Pfaffenlehner, J. Lutz
{"title":"The influence of bulk parameters on the switching behavior of FWDs for traction application","authors":"H. Felsl, E. Falck, M. Pfaffenlehner, J. Lutz","doi":"10.1109/ICMEL.2004.1314577","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314577","url":null,"abstract":"We investigate the performance of free wheeling diodes (FWDs) for traction application. Since there is experimental evidence of well designed junction termination, we concentrate on bulk effects. By numerical simulation the influence of bulk doping and base width on the dynamic characteristics of FWDs is analyzed. As limiting criterium for snap-off behavior the reach-through of the space-charge region to the nn/sup +/-emitter region is found. Measurements are in good agreement with the simulations.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Characterization and modelling issues in MOS structures with ultra thin oxides 超薄氧化物MOS结构的表征与建模问题
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314566
G. Ghibaudo, R. Clerc
{"title":"Characterization and modelling issues in MOS structures with ultra thin oxides","authors":"G. Ghibaudo, R. Clerc","doi":"10.1109/ICMEL.2004.1314566","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314566","url":null,"abstract":"A review of the main modeling and electrical characterization issues in MOSFETs with ultra gate oxides is presented. In a first part, advances in the modeling of polydepletion in the gate and quantum confinement in the substrate are analyzed and their impacts on the parameter extraction from electrical measurements and numerical simulations are discussed. Moreover, the impact of gate leakage on capacitance measurements is carefully analyzed and procedures to overcome these parasitic effects are introduced. Finally, the implication of gate leakage partitioning between source and drain is addressed both experimentally and theoretically for MOSFET characterization purposes.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Photoacoustic spectroscopy: investigation of sputter damage in Si surface by Ar plasma 光声光谱:氩等离子体溅射损伤硅表面的研究
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314853
D. Todorović, M. Smiljanić, M. Sarajlić, D. Vasiljević-Radović, Danijela Randjelovic
{"title":"Photoacoustic spectroscopy: investigation of sputter damage in Si surface by Ar plasma","authors":"D. Todorović, M. Smiljanić, M. Sarajlić, D. Vasiljević-Radović, Danijela Randjelovic","doi":"10.1109/ICMEL.2004.1314853","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314853","url":null,"abstract":"The effect of Ar plasma etching on the surface of Si was investigated by photoacoustic spectroscopy. The surface of Si sample (p-tip, 10 k/spl Omega/cm, 420 /spl mu/m) was treated with Ar plasma from 2 min to 80 min. Amplitude and phase PA spectra were measured in the energy range from 0.75 to 1.55 eV. The amplitude ratio and phase difference of photoacoustic signals of Si samples Ar plasma etched and incoming Si samples indicate existence of two surface energy states (the generation-recombination centers) at 0.31 and 0.99 eV.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128867435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical properties and conduction mechanisms in Hf/sub x/Ti/sub y/Si/sub z/O films obtained from novel MOCVD precursors 新型MOCVD前驱体制备的Hf/sub x/Ti/sub y/Si/sub z/O薄膜的电学性能和传导机制
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314650
A. Paskaleva, M. Lemberger, S. Zurcher, A. Bauer
{"title":"Electrical properties and conduction mechanisms in Hf/sub x/Ti/sub y/Si/sub z/O films obtained from novel MOCVD precursors","authors":"A. Paskaleva, M. Lemberger, S. Zurcher, A. Bauer","doi":"10.1109/ICMEL.2004.1314650","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314650","url":null,"abstract":"We have investigated electrical behaviour of high-k Hf/sub x/Ti/sub y/Si/sub z/O layers with different Hf:Ti ratios in the film. The films are prepared by MOCVD using novel single-source precursors. Oxide and interface charges, leakage currents and conduction mechanisms are found to be a strong function of the film composition. The films with lower Hf content show lower level of oxide and interface charges and higher dielectric constant whereas those with higher Hf content have better leakage current properties. It is established that in the films with lower Hf content the conduction is governed by a phonon-assisted process, i.e. it is defined rather by the intrinsic properties of the layer than by its defect structure.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical-based non-quasi static MOSFET model for DC, AC and transient circuit analysis 基于物理的非准静态MOSFET模型，用于直流、交流和瞬态电路分析
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314611
T. Pesic, N. Jankovic
{"title":"Physical-based non-quasi static MOSFET model for DC, AC and transient circuit analysis","authors":"T. Pesic, N. Jankovic","doi":"10.1109/ICMEL.2004.1314611","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314611","url":null,"abstract":"In this paper, we describe a compact physical-based non-quasi static (NQS) MOST model for SPICE. Based on the comparison with results of 2-D device simulations, it is shown that new NQS model can accurately predict NMOST behavior during DC, AC and transient operation.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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