Edge effect under temperature bias stress of 0.18 /spl mu/m PMOS technology

Edge effects under positive and negative bias temperature stress (PBTI and NBTI) of 0.18 /spl mu/m PMOS technology are quantified in terms of the parasitic source-drain series resistance. For the first time it is demonstrated that the series resistance degradation under NBTI is channel length independent although the shift in absolute parameter change increases with reducing channel length. Under NBTI the threshold voltage shifts towards more negative values. The damage mechanism is predominantly by donor type interface states, with a minor contribution of bulk traps. Under PBTI, damage in the centre of the channel, attributed to electron traps causes a shift in threshold voltage towards more positive values, whereas donor type interface states generated towards the edge of the channel contribute to a minor increase in series resistance. PBTI causes lesser damage in comparison to NBTI.