Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献_第4页

Formal design verification for correctness of pipelined microprocessors with out-of-order instruction execution 具有乱序指令执行的流水线微处理器正确性的正式设计验证

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759989

Takashi Takenaka, J. Kitamichi, T. Higashino, K. Taniguchi

引用次数: 0

Interconnect delay estimation models for synthesis and design planning 用于综合和设计规划的互连延迟估计模型

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759720

J. Cong, D. Pan

引用次数: 58

Optimal evaluation clocking of self-resetting domino pipelines 自复位多米诺骨牌管道的最优评估时钟

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759728

K. Yun, Ayoob E. Dooply

引用次数: 7

An SA-based nonlinear function synthesizer for linear analog integrated circuits 线性模拟集成电路的非线性函数合成器

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759697

Huazhong Yang, Rong Luo, Hui Wang, Runsheng Liu

引用次数: 0

EDA Roadmap and Future VLSI Design Technology Enhancement EDA路线图和未来VLSI设计技术的改进

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760037

T. Hiwatashi

引用次数: 0

Package market segments and design challenges 包装细分市场和设计挑战

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760044

R. Bracken

{"title":"Package market segments and design challenges","authors":"R. Bracken","doi":"10.1109/ASPDAC.1999.760044","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760044","url":null,"abstract":"In the development of the 1997 edition of the National Technology Roadmap for Semiconductors (NTRS), the Roadmap Coordinating Group (RCG) recognized the needs of the semiconductor industry for larger chips having higher speed and power, and greater transistor density. The overall consensus is that the industry had over-run the present Roadmap Technology projections by about 1-2 years. From these projections of the overall technology characteristics are derived for the needs for packaging and assembly technologies that support and enable this dynamic growth. In the present paper, we shall provide detailed discussions of the potential solutions for the high density substrates and the issues that the wafer development brings to the creation of packaging solutions for future electronic systems. The most apparent changes to the packaging technology requirements changes have been driven by the increase in chip speed and functionality, the materials set for wafer level interconnect, and the power requirements. These quantities have driven the derived needs for greater and greater interconnect to and from the chip, different materials for packaging solutions, more effective thermal management, and software systems to design and model it all. The package is also shrinking to meet the miniaturization requirements of many of the hand-held products. The most challenging issue is the cost of the packaging solutions, which has generally exceeded the targets desired by users. Additional invention and/or development will be needed before the needed packaging can be deployed as affordable solutions.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132168294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A scalable pipelined architecture for separable 2-D discrete wavelet transform 二维离散小波变换的可扩展流水线结构

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759996

J. Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang

引用次数: 7

Timing optimization of logic network using gate duplication 基于门重复的逻辑网络时序优化

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760003

Chun-hong Chen, C. Tsui

引用次数: 20

An 8 b 52 MHz double-channel CMOS A/D converter for high-speed data communications 用于高速数据通信的8b 52 MHz双通道CMOS A/D转换器

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759701

Juhee Kim, Sungkil Hwang, Seunghoon Lee, Y. Jee

引用次数: 1

Solving the rectangular packing problem by an adaptive GA based on sequence-pair 基于序列对的自适应遗传算法求解矩形装箱问题

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759990

Koichi Hatta, S. Wakabayashi, T. Koide

引用次数: 25