An 8 b 52 MHz double-channel CMOS A/D converter for high-speed data communications

Abstract

This paper describes an 8 b 52 MHz CMOS subranging analog-to-digital converter for Integrated Services Digital Network applications. The ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs for an increased throughput rate. The fabricated and measured prototype ADC in a 0.8 /spl mu/m CMOS process shows nonlinearities less than /spl plusmn/0.4 LSB at an 8 b level with 5 V and 230 mW.