Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献

An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection 具有动态交叉算子选择的自适应遗传算法的大规模集成电路实现

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759704

S. Wakabayashi, T. Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta

引用次数: 6

An automatic router for the pin grid array package 一个用于引脚网格阵列的自动路由器包

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759783

Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai

引用次数: 15

Electrical design and design automation for packaging 电气设计和包装设计自动化

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760045

D. Becker

{"title":"Electrical design and design automation for packaging","authors":"D. Becker","doi":"10.1109/ASPDAC.1999.760045","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760045","url":null,"abstract":"One important challenge in the electrical design of electronic packaging is encountered in the many systems requiring processors operating at clock frequencies in the hundreds of Megahertz. The competition to provide higher performance computers results in an increasing number of processors in a system and these processors are running at faster clock frequencies. The package needs to support wider buses at higher frequencies to connect the processors with each other and with cache and main memory data storage. Since the interconnects must run without interruption, the timing and noise characteristics of these paths must be characterized and managed. The short design cycle is supported by including the management of the timing and noise characteristics as an integral part of the high-level system design at the beginning of the project and then verifying that the same constraints are met for the formal design review before the finished designs are released into manufacturing. The principles we follow to design the packaging for multi-processor systems are presented. A methodology for design will be described which defines budgets and equations to efficiently calculate the timing and noise on the interconnects. This provides a means to include the electrical considerations in the optimal cost-performance choice of technology. The budgets and equations are then integrated into the design tools and provide guidance in the design of the power and signal distribution and the means for thorough post-design verification of the electrical performance of the package in the system.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent advances in asynchronous design methodologies 异步设计方法的最新进展

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760008

K. Yun

引用次数: 2

Design and optimization of power/ground network for cell-based VLSIs with macro cells 具有宏单元的基于单元的vlsi电源/地网络的设计与优化

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759700

Xiaohai Wu, Changge Qiao, Xianlong Hong

引用次数: 9

Minimization of free BDDs 最小化空闲bdd

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760024

Wolfgang Günther, R. Drechsler

引用次数: 46

Model order reduction of large circuits using balanced truncation 使用平衡截断的大型电路模型降阶

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760004

P. Rabiei, Massoud Pedram

引用次数: 54

A new pipelined architecture for fuzzy color correction 一种新的模糊色彩校正流水线结构

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759997

J. Jou, Shiann-Rong Kuang, Yeu-Horng Shiau

引用次数: 0

A performance-driven I/O pin routing algorithm 一个性能驱动的I/O引脚路由算法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759779

Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen

{"title":"A performance-driven I/O pin routing algorithm","authors":"Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen","doi":"10.1109/ASPDAC.1999.759779","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759779","url":null,"abstract":"This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on a min-cost max-flow algorithm is proposed. In this phase, an exponential weight function is used to guide the flow distribution which is very helpful in distributing wires, globally and uniformly, on the whole routing area. Then a physical routing phase is applied to implement one-to-one connection between chip pads and I/O pins, which focuses on the wire uniformity of the fanout area nearby the periphery of chip pads. Finally, a balanced position based wire polishing approach is proposed to further improve the local wire uniformity which tries to modify each wire into a smooth curve instead of broken line while satisfying the specified design rules such as wire-wire pitch and wire-pin pitch. A routing cost function is adequately defined to guide the whole routing process which leads to a good trade-off between wire uniformity and wire length. The algorithm has been implemented and tested on up to 10-ring 600-pin PGA and the experimental results are very promising.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131876613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Universal switched-current integrator blocks for SI filter design 用于SI滤波器设计的通用开关电流积分器模块

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760009

J. Chan, S. Chung

引用次数: 0