Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献_第10页

VCO jitter simulation and its comparison with measurement VCO抖动仿真及其与测量值的比较

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759717

Masayuki Takahashi, Kimihiro Ogawa, K. Kundert

引用次数: 57

Application driven variable reordering and an example implementation in reachability analysis 应用程序驱动的变量重排序和可达性分析中的一个示例实现

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760025

C. Meinel, Klaus Schwettmann, A. Slobodová

引用次数: 5

A new numerical method for transient noise analysis of nonlinear circuits 非线性电路暂态噪声分析的一种新的数值方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759986

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, B. Mulvaney

引用次数: 3

VCDS: virtual core based design system 基于虚拟核心的设计系统

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760041

M. Muraoka

{"title":"VCDS: virtual core based design system","authors":"M. Muraoka","doi":"10.1109/ASPDAC.1999.760041","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760041","url":null,"abstract":"The Design Productivity Crisis of LSI towards 2010 have been discussed for a few years especially in SEMATECH, USA. The innovation of LSI design methodology will be the most effective way to resolve the issues of the design crisis. SIRIJ, Semiconductor Industry Research Institute Japan, has organized 'VCDS Committee' to research the next generation EDA system towards 2010. 'VCDS: Virtual Core based Design System' is proposed as the next generation EDA system to solve the issues of the design crisis. VCDS provides designers with VCs: Virtual Cores and the VC based design methodology to reduce the design time and the power consumption of system LSI for electronic systems drastically. VCDS technologies are based on hardware/software codesign and IP re-use methodologies. VCDS consists of VCDB (VC Data Base), VCPF (VC Platform), System Synthesizer and VC Synthesizer. VCDB stores high level and flexible IPs called VCs (Virtual Cores). The VCs are defined as abstract and flexible functionality at system level and are categorized by the application domains. The designer stores VCs in the VCDB by use of the registration tool of VCPF and search and instantiate them from the database via VCPF. System Synthesizer of VCDS consists of system specification definition tools, evaluation tools for hardware/software tradeoff and validation/verification, optimization tools for hardware/software codesign, the generation tools for system architecture, and the software generation tools for software compiler and software development environment. The generated system architecture consists of hardware VCs and software VCs. VC Synthesizer generates the physical design of each VC in the system architecture. VCDS is proposed as the next generation EDA system to make the solution of the coming design crisis. VCDS makes designers to define the system specification by selecting system level VCs and decide the optimum combination of hardware/software efficiently.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

The design of delay insensitive asynchronous 16-bit microprocessor 延时不敏感异步16位微处理器的设计

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759703

Byun-Soo Choi, Dong-Wook Lee, Dong-Ik Lee

引用次数: 1

Optimization of linear placements for wirelength minimization with free sites 优化线性放置的无线最小与自由站点

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760005

A. Kahng, P. Tucker, A. Zelikovsky

引用次数: 83

An efficient two-level partitioning algorithm for VLSI circuits VLSI电路的高效两级划分算法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759712

Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho

{"title":"An efficient two-level partitioning algorithm for VLSI circuits","authors":"Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho","doi":"10.1109/ASPDAC.1999.759712","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759712","url":null,"abstract":"In this paper, a new two-level bipartitioning algorithm TLP, combining a hybrid clustering technique with an iterative improvement based partitioning process, is proposed. The hybrid clustering algorithm consisting of a local bottom-up clustering technique to merge modules and a global top-down ratio-cut technique for decomposition can be used to reduce the partitioning complexity and improve the performance. To generate a high-quality partitioning solution, a module migration based partitioning algorithm MMP is also proposed as the base partitioner for the TLP algorithm. The MMP algorithm implicitly promotes the move of clusters during the module migration processes by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Experimental results obtained show that the TLP algorithm generates stable and high-quality partitioning results. The TLP algorithm improves the unstable property of module migration based algorithms such as FM and STABLE in terms of the average net cut value. On the other hand, TLP outperforms MELO, GFM/sub t/ and CDIP/sub LA3/ by 23%, 7%, and 10%, respectively and is competitive with hMetis, ML/sub c/ and LSR/MFFS which have generated better results than many recent state-of-the-art partitioning algorithms.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Estimation of peak current through CMOS VLSI circuit supply lines 通过CMOS VLSI电路供电线路估计峰值电流

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1998-09-22 DOI: 10.1109/ASPDAC.1999.760017

T. Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi

{"title":"Estimation of peak current through CMOS VLSI circuit supply lines","authors":"T. Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi","doi":"10.1109/ASPDAC.1999.760017","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760017","url":null,"abstract":"We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based algorithm to obtain a tight lower bound. In order to handle sequential circuits, we equate latch outputs with primary inputs for the upper bound estimation and use a logic simulator to determine the initial values for the lower bound estimation. Based on the information obtained, we model all blocks in the circuit as voltage-controlled current sources, with the analog hardware description language (AHDL). After extracting parasitic resistances of the power supply lines, we simulate the entire circuit using an analog simulator and obtain the maximum current estimation and voltage drops in the supply lines. In the modeling procedure we take the negative feedback influence into consideration such that the estimated current reflects a real switching transition. We have implemented the theoretically modeled negative feedback influence into our simulator called PANGI. Some experimental results of applying PANGI to the circuits which consist of more than 1M gates prove the accuracy and reliability of our approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Node sampling technique to speed up probability-based power estimation methods 节点采样技术加速了基于概率的功率估计方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1998-06-25 DOI: 10.1109/ASPDAC.1999.759984

Hoon Choi, Hansoo Kim, I. Park, S. Hwang, C. Kyung

引用次数: 0

Roadmap organization and activities in Japan 在日本的路线图组织和活动

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1900-01-01 DOI: 10.1109/ASPDAC.1999.760038

Y. Furui

引用次数: 0