Estimation of peak current through CMOS VLSI circuit supply lines

We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based algorithm to obtain a tight lower bound. In order to handle sequential circuits, we equate latch outputs with primary inputs for the upper bound estimation and use a logic simulator to determine the initial values for the lower bound estimation. Based on the information obtained, we model all blocks in the circuit as voltage-controlled current sources, with the analog hardware description language (AHDL). After extracting parasitic resistances of the power supply lines, we simulate the entire circuit using an analog simulator and obtain the maximum current estimation and voltage drops in the supply lines. In the modeling procedure we take the negative feedback influence into consideration such that the estimated current reflects a real switching transition. We have implemented the theoretically modeled negative feedback influence into our simulator called PANGI. Some experimental results of applying PANGI to the circuits which consist of more than 1M gates prove the accuracy and reliability of our approach.