Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献_第9页

A method for evaluating upper bound of simultaneous switching gates using circuit partition 一种利用电路划分求同时开关门上界的方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760016

Kai Zhang, T. Shinogi, H. Takase, T. Hayashi

引用次数: 4

Reduced-order modelling of time-varying systems 时变系统的降阶建模

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759708

J. Roychowdhury

引用次数: 47

Fast instruction cache simulation strategies in a hardware/software co-design environment 硬件/软件协同设计环境下的快速指令缓存仿真策略

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760030

M. Lajolo, L. Lavagno, A. Sangiovanni-Vincentelli

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引用次数: 12

An efficient structural approach to board interconnect diagnosis 一种板互连诊断的有效结构方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760020

C. Lo, Philip C. H. Chan

引用次数: 1

Enhancing the efficiency of reduction of large RC networks by pole analysis via congruence transformations 基于同余变换的极点分析提高了大型RC网络的约简效率

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759718

Zheng Hui, Z. Wenjun, Tian Li-lin, Yang Zhilian

引用次数: 0

Realization of regular ternary logic functions using double-rail logic 用双轨逻辑实现正则三元逻辑函数

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760026

Y. Iguchi, M. Matsuura, Tsutomu Sasao, Atsumu Iseno

引用次数: 8

Clock period minimization of semi-synchronous circuits by gate-level delay insertion 通过门级延迟插入实现半同步电路时钟周期最小化

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759775

T. Yoda, A. Takahashi, Y. Kajitani

引用次数: 14

Waveform relaxation of linear integral-differential equations for circuit simulation 电路仿真中线性积分-微分方程的波形松弛

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759710

Yaolin Jiang, O. Wing

引用次数: 6

FSM modeling of synchronous VHDL design for symbolic model checking FSM建模的同步VHDL设计，用于符号模型的校核

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760034

Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, X. Hong

引用次数: 3

Testing interconnects of dynamic reconfigurable FPGAs 动态可重构fpga互连测试

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760013

Chi-Feng Wu, Cheng-Wen Wu

引用次数: 4