FSM建模的同步VHDL设计，用于符号模型的校核

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.760034

Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, X. Hong

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引用次数: 3

摘要

本文基于同步行为和符号表示技术，定义了一种新的FSM模型。提出了用同步电路的VHDL描述来细化模型的算法。通过消除不必要的过渡函数，我们的模型比Deharbe的混合模型具有更少的状态。实验结果表明，该模型和建模方法可以使符号模型检验更加实用。

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FSM modeling of synchronous VHDL design for symbolic model checking

In this paper, we defined a new FSM model based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnecessary transition function, our model has much less states than Deharbe's mixed model. The experimental results demonstrate the model and modeling method can make symbolic model checking more practical.

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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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