一种利用电路划分求同时开关门上界的方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.760016

Kai Zhang, T. Shinogi, H. Takase, T. Hayashi

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引用次数: 4

摘要

本文提出了一种计算组合电路中同时开关门上限的方法。该方法将原电路划分为子电路，并将其上界近似计算为所有子电路的最大开关门之和。为了提高精度，我们采用了一种同时考虑子电路间互连和生成子电路数量的评估函数。ISCAS电路的实验结果表明，该方法能有效地评估开关门的上界。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A method for evaluating upper bound of simultaneous switching gates using circuit partition

This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates.

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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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