一个用于引脚网格阵列的自动路由器包

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.759783

Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai

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引用次数: 15

摘要

介绍了一种PGA封装路由器。给定一个芯片腔，在其边界周围有多个I/O焊盘和分布在基板上的等量引脚，路由器的目标是在一个或多个层上完成焊盘到引脚网的平面互连。该路由器由三个阶段组成:层分配、拓扑路由和几何路由。在基于windows的环境下测试的实例表明，我们的路由器是高效的，可以用较少的基板层完成路由任务。与手动路由相比，该路由器具有友好的图形用户界面，可以实际应用于VLSI封装。

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An automatic router for the pin grid array package

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router features a friendly graphic user interface and can be practically applied to VLSI packaging.

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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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