{"title":"Layout-based logic decomposition for timing optimization","authors":"Yun-Yin Lian, Y. Lin","doi":"10.1109/ASPDAC.1999.760002","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760002","url":null,"abstract":"As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes dominated by the interconnect delay. In a traditional top-down design flow, logic synthesis algorithms optimize gate area or delay without accurate interconnect delay because of lack of physical design information. Thus, the effectiveness of the optimization techniques is limited. We integrate logic synthesis and physical design into an iterative procedure for performance optimization. The logic synthesis process can optimize circuit delay based on accurate interconnect delay information extracted from the physical design. The physical design tools can refine the layout incrementally with the engineering change information and changed netlist passed from the logic synthesis process. In this thesis, we integrate logic decomposition, gate sizing and buffer insertion to work together to improve the circuit speed. Experimental results on a set of benchmark circuits show that the techniques are indeed effective.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129490120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis","authors":"S. Tan, C. Shi","doi":"10.1109/ASPDAC.1999.759572","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759572","url":null,"abstract":"Symbolic analysis of analog circuits is important in analog design automation. However, it is limited to the analysis of small analog circuits where exact symbolic expressions are required. In this paper, we present an efficient algorithm for partitioning large general analog circuits into smaller subcircuits so that symbolic analysis can be performed hierarchically. Experimental results have demonstrated that our method outperforms the best partitioning-based symbolic analyzer SCAPP.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126204856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An adaptive BIST to detect multiple stuck-open faults in CMOS circuits","authors":"H. Rahaman, D. K. Das, B. Bhattacharya","doi":"10.1109/ASPDAC.1999.760015","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760015","url":null,"abstract":"Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average length of the test sequence (TS) in an n-input CUT is (n+1).2/sup n/ [(n+1).2/sup n-1/] in a fault-free [faulty] condition. The response analyzer (RA) is also simple to design. All robustly testable multiple stuck-open faults (occurring simultaneously both in n- and p-parts) can be detected using the proposed BIST scheme.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123106935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal/mechanical design and design automation for packaging","authors":"R. Mahajan","doi":"10.1109/ASPDAC.1999.760046","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760046","url":null,"abstract":"The need for mechanical and thermal analysis/synthesis is motivated through examples of applications. The development cycle for design is discussed in some detail and the criticality of comprehensive analysis to ensure successful design is discussed. It is demonstrated that successful integration of diverse functional and reliability requirements requires thorough studies of design options. The current state of the art in design synthesis and analysis tools is reviewed. It is suggested that design tools still need improvements in connectivity between electrical layout and thermal and mechanical analysis/synthesis tools. Another issue that needs greater emphasis is the issue of dimensional scale transitions in analyses at the die level vs those at the package and system levels. Both these issues are reviewed in context of the ability of current tools. Some challenges as we go forward are identified based on this review.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122294928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data path synthesis for BIST with low area overhead","authors":"Xiaowei Li, P. Cheung","doi":"10.1109/ASPDAC.1999.760012","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760012","url":null,"abstract":"This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demonstrate the effectiveness of the proposed data path synthesis for BIST approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125129043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power CMOS off-chip drivers with slew-rate difference","authors":"Rung-Bin Lin, Jinq-Chang Chen","doi":"10.1109/ASPDAC.1999.759987","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759987","url":null,"abstract":"This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates to the P and N channel transistors that drive the output pad. The slew rates are deliberately designed such that the N(P) transistor at the output stage will be turned off faster than the P(N) transistor is turned on for low-to-high (high-to-low) output transitions. It is demonstrated experimentally by HSPICE simulation that the off-chip driver designed by the proposed approach not only produces viable power-delay products, but also results in smaller noise.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient iterative improvement technique for VLSI circuit partitioning using hybrid bucket structures","authors":"C. Eem, J. Chong","doi":"10.1109/ASPDAC.1999.759713","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759713","url":null,"abstract":"In this paper, we present a fast and efficient iterative improvement partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to their time efficiency, IIP algorithms are widely used in VLSI circuit partitioning. As the performance of these algorithms depends on choices of moving cells, various such methods have been proposed. In particular, the cluster-removal algorithm by S. Dutt significantly improved partition quality. We indicate the weaknesses of previous algorithms using a uniform method for the choice of cells during improvement. To solve this problem, we propose a new IIP technique that selects the method for choice of cells according to improvement status and presents hybrid bucket structures for easy implementation. The time complexity of the proposed algorithm is the same as the FM method, and the experimental results on ACM/SIGDA benchmark circuits show improvement up to 33-44%, 45-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with shorter CPU time, our technique outperforms Paraboli and MELO represented constructive partition methods by about 12% and 24%, respectively.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power consumption in XOR-based circuits","authors":"Y. Ye, K. Roy, R. Drechsler","doi":"10.1109/ASPDAC.1999.760018","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760018","url":null,"abstract":"The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR dominated logic. Due to different possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively. Power dissipation due to (charging and discharging) internal node capacitances is also considered.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"775 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133648077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast Boolean matching under permutation using representative","authors":"D. Debnath, Tsutomu Sasao","doi":"10.1109/ASPDAC.1999.760033","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760033","url":null,"abstract":"This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an ordinary workstation, on the average, our method requires several microseconds to test the Boolean matching for functions with up to eight variables. This approach is promising for Boolean matching of multiplexor-based field-programmable gate arrays (FPGAs) and for library matching with many large cells.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134487365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jin-Kug Lee, D. Chang, Geun-Soon Kang, Seunghoon Lee
{"title":"A single-chip CMOS CCD camera interface circuit with digitally controlled AGC","authors":"Jin-Kug Lee, D. Chang, Geun-Soon Kang, Seunghoon Lee","doi":"10.1109/ASPDAC.1999.759706","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759706","url":null,"abstract":"This paper describes a single-chip solution for CMOS CCD camera interface systems. The required AGC gain in the proposed circuit is controlled directly by digital bits without conventional extra DAC's. Nonlinear errors such as offsets in signal paths are automatically removed during black-level correction. The AGC outputs are transferred to a 10 b on-chip ADC. The prototype implemented in a 0.5 /spl mu/m n-well CMOS process shows the 32-dB AGC dynamic range CMOS process shows the 32-dB AGC dynamic range in 1/8-dB step with 173 mW at 3 V and 25 MHz.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}