Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献_第3页

Hazard-free synthesis and decomposition of asynchronous circuits 异步电路的无害化合成与分解

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759991

Ren-Der Chen, J. Jou, Yeu-Horng Shiau

引用次数: 0

Technology mapping for low power 低功耗技术映射

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759981

C. Yeh, C. Chang, Jinn-Shyan Wang

引用次数: 6

A new technique to exploit frequency domain latency in harmonic balance simulators 一种利用谐波平衡模拟器频域延迟的新技术

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759711

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, K. Gullapalli, B. Mulvaney

引用次数: 3

An efficient approach to constrained via minimization for two-layer VLSI routing 一种有效的两层VLSI路由约束最小化方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759982

Maolin Tang, K. Eshraghian, H. Cheung

引用次数: 18

Embedded tutorial: hardware/software codesign 嵌入式教程:硬件/软件协同设计

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760042

M. Imai

引用次数: 2

Generation of interpretive and compiled instruction set simulators 生成解释和编译指令集模拟器

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760028

R. Leupers, Johann Elste, Birger Landwehr

引用次数: 56

Relaxed simulated tempering for VLSI floorplan designs VLSI平面设计的轻松模拟回火

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759698

J. Cong, T. Kong, D. Xu, F. Liang, Jun S. Liu, W. Wong

引用次数: 17

A US/Japan comparison of design/EDA capabilities 美国/日本设计/EDA能力的比较

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760040

H. Mayumi

{"title":"A US/Japan comparison of design/EDA capabilities","authors":"H. Mayumi","doi":"10.1109/ASPDAC.1999.760040","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760040","url":null,"abstract":"The time is nearing when every ordinary engineer can design his favorite functions into LSI; however it may require drastic reformations in design technology and in social infrastructure. In this survey we evaluate and analyze Japanese design capability relative to the USA's, proposing possible suggestions to prepare for such reformations. Complexity of LSI is measured by an adequately normalized transistor count (NTC), then 'design productivity' is defined as NTC per person-week. Seven factors influencing design capability are selected: team, management, EDA, reuse, business, specification and implementation. 21 ASSP design teams (11 Japanese, 10 US) were chosen and interviewed based on a detailed questionnaire on these metrics/factors, and the acquired data compared by US/Japan averages. NTC ranges around from 100 K to 2 M, averaging at 700 K in both countries. Japanese (J) 'productivity' is a bit higher while its 'production rate (NTC per week)' is lower (losing TTM) than USA's. Factor analysis indicates (all the figures are normalized by NTC): J team size is half of US's; J spends bigger money on EDA and longer time in simulation, but shorter time in verification; J consumes 2.5 times more respins; J loses much more TTM, in more than half the cases due to manager-controllable factors such as design bug, design spec, change, and process tech change. Derived suggestions for Japan are: double the number of engineers per team; reexamine design management in order to reduce fatal bugs and respins; improve EDA quality and reuse quantity; examine and solve perception gaps between managers and engineers about their targets like high quality, reuse, and TTM.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131623751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high speed and low power phase-frequency detector and charge-pump 一种高速低功率相频检测器和电荷泵

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760011

W. Lee, Jun-Dong Cho, S. Lee

{"title":"A high speed and low power phase-frequency detector and charge-pump","authors":"W. Lee, Jun-Dong Cho, S. Lee","doi":"10.1109/ASPDAC.1999.760011","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760011","url":null,"abstract":"In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is over 1.2 GHz without additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01 ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent from the duty cycle of input signals. A new charge-pump circuit is presented that is designed using a charge-amplifier. A stand-by current enhances the speed of charge-pump and removes the charge-sharing which causes a phase noise in the charge-pump PLL. Also, the effects of clock feed-through are reduced by separating the output stage from UP and down signal. The simulation results base on a third-order PLL are presented to verify the lock-in process with the proposed PFD and charge-pump circuits. The PFD and charge-pump circuits are designed using 0.8 /spl mu/m CMOS technology with 5 V supply voltage.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132934492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 94

Design re-use: where is the productivity going to come from? 设计重用:生产力从何而来?

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760048

J. Ahuja

引用次数: 0