Hazard-free synthesis and decomposition of asynchronous circuits

Abstract

In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations.