一种有效的两层VLSI路由约束最小化方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.759982

Maolin Tang, K. Eshraghian, H. Cheung

{"title":"一种有效的两层VLSI路由约束最小化方法","authors":"Maolin Tang, K. Eshraghian, H. Cheung","doi":"10.1109/ASPDAC.1999.759982","DOIUrl":null,"url":null,"abstract":"Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"An efficient approach to constrained via minimization for two-layer VLSI routing\",\"authors\":\"Maolin Tang, K. Eshraghian, H. Cheung\",\"doi\":\"10.1109/ASPDAC.1999.759982\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.\",\"PeriodicalId\":201352,\"journal\":{\"name\":\"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1999.759982\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1999.759982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 18

摘要

通过最小化约束的问题是重新分配VLSI路由的线段，以便使过孔的数量最小化。本文提出了一种双层VLSI路由的新方法。这种方法能够处理任何类型的路由，并允许任意数量的线段在一个via候选点上分裂。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An efficient approach to constrained via minimization for two-layer VLSI routing

Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

自引率

0.00%

发文量