Technology mapping for low power

Abstract

Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several research attentions. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern oriented power modeling for improved technology mapping. We first perform a profitability study using the complete pattern to pattern transition data organized in tabular form. Then, we propose a probability-based, pattern oriented technology mapping method. Empirical results on benchmark circuits demonstrate the proposed method delivered an average of 13% power reduction compared to the traditional mapping method.