Formal design verification for correctness of pipelined microprocessors with out-of-order instruction execution

Abstract

In this paper, we propose a verification method for pipelined microprocessors with out-of-order execution. We define a class of pipelined microprocessors with out-of-order execution and give a sufficient condition that guarantees the correctness of implementation. Each microprocessor in this class has a pipeline stg/sub 1/,...,stg/sub n/ such that the stages stg/sub c/,...,stg/sub n/ are so-called "in-order pipeline" and changes the execution order of instructions within the stages of stg/sub 1/,...,stg/sub c-1/. Using our method, we carried out the correctness proof of a practical 6-stage pipelined microprocessor that has a so-called scoreboard. We used a verifier having a decision procedure for Presburger sentences. The total CPU time spent in the proof was about 8 hours.