{"title":"A technology-independent methodology of placement generation for analog circuit","authors":"W. Wong, Philip C. H. Chan, Wai-on Law","doi":"10.1109/ASPDAC.1999.759980","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759980","url":null,"abstract":"An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented. A novel optimization approach based on circuit partitioning, simulated annealing and a branch-and-bound algorithm is proposed to solve the placement problem. The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration. Results of two silicon proven designs generated by the system demonstrate an 8X cycle time reduction as compared to a manual approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the testing quality of random and pseudo-random sequences for permanent and intermittent faults","authors":"Jin Ding, Yu-Liang Wu","doi":"10.1109/ASPDAC.1999.760021","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760021","url":null,"abstract":"In this paper, the natures of random and pseudo-random input sequences and their influence on permanent and intermittent fault detecting are analyzed. The aliasing fault coverage between the pseudo-random and random sequences is estimated. The activity probability features of the intermittent faults are considered. The self-test circuits of the intermittent faults are illustrated. The experimental results based on real circuits are obtained through simulation. The mathematical analysis and experimental results show that the quality of the pseudo-random testing is better than that of the random testing for permanent and intermittent faults. The Markov chain models are used in obtaining the input sequence length needed for determining if a circuit fault is intermittent or permanent.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Combining speculative execution and conditional resource sharing to efficiently schedule conditional behaviors","authors":"A. Kountouris, C. Wolinski","doi":"10.1109/ASPDAC.1999.760029","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760029","url":null,"abstract":"Scheduling conditional behaviors necessitates the use of a variety of scheduling optimization techniques like conditional resource sharing and speculative execution. Previous research work has clearly shown their effectiveness. The developed heuristics have several drawbacks relating to the effects of syntactic variance on the results. In this paper a list-based scheduling heuristic that exploits conditional resource sharing and speculative execution possibilities, is presented. Its results are quite insensitive to syntactic variance and conditional behavior is effectively accounted for by a probabilistic priority function.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Slicing floorplans with boundary constraint","authors":"Evangeline F. Y. Young, D. F. Wong","doi":"10.1109/ASPDAC.1999.759699","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759699","url":null,"abstract":"In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117287411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EDA Roadmap in Japan","authors":"T. Hiwatashi","doi":"10.1109/ASPDAC.1999.760039","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760039","url":null,"abstract":"The system LSI design in the future would be focused on an entire design procedure from algorithm design through physical implementation design. Revolutionary design methodologies are required from various aspects, such as software design accomplished in parallel with hardware design, built-in analog/sensor functionality of human interface and shorter time-to-market design style because of shorter product life cycle. Under the above situation, EDA Technical Committee in EIAJ (Electronic Industries Association of Japan) organized \"EDA Vision Working Group\" for investigation of desired design methodologies of system LSIs in 2002. Started in September 1996, the working group has completed \"EDA Technology Roadmap Toward 2002\". The working group defined targeted system LSIs called \"Cyber-Giga-Chip\", which will be widely used in consumer portable information applications, and would be the major products in domestic semiconductor industry. EDA needs and corresponding requirements are studied through detailed interviews with advanced experts of LSI designers as well as EDA engineers. \"EDA Technology Roadmap Toward 2002\" finally summarizes those EDA requirements into a set of roadmaps which indicates potential To Be solutions needed toward 2002 or beyond. In the session, some essential contents and results in \"EDA Technology Roadmap Toward 2002\" will be presented, and also successive activities with EDA Roadmap in Japan addressed.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131741230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sakurai, Mizuki Takahashi, A. Kay, A. Yamada, T. Fujimoto, T. Kambe
{"title":"A scheduling method for synchronous communication in the Bach hardware compiler","authors":"R. Sakurai, Mizuki Takahashi, A. Kay, A. Yamada, T. Fujimoto, T. Kambe","doi":"10.1109/ASPDAC.1999.759993","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759993","url":null,"abstract":"In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A genetic algorithm based approach for multi-objective data-flow graph optimization","authors":"Birger Landwehr","doi":"10.1109/ASPDAC.1999.760032","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760032","url":null,"abstract":"This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow graphs (DFG) which ensures that the correctness of algebraic transformations realized by the underlying genetic operators selection, recombination, and mutation is always preserved. We present substantial fitness functions for both the minimization of overall resource costs and critical path length. We also demonstrate that, due to their flexibility, genetic algorithms can be simply adapted to different objective functions which is shown for power optimization. In order to avoid inferior results caused by the counteracting demands on resources of different basic blocks, all DFGs of the input description are optimized concurrently. Experimental results for several standard benchmarks prove the efficiency of our approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting don't cares during data sequencing using genetic algorithms","authors":"R. Drechsler, Nicole Drechsler","doi":"10.1109/ASPDAC.1999.760019","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760019","url":null,"abstract":"In this paper we present a Genetic Algorithm (GA) for the Data Ordering Problem (DOP) where Don't Cares (DCs) are assigned during optimization. The DOP has large application in the area of low power design and circuit testing. We implemented a GA to solve this problem and discuss several applications. We carried out a large set of experiments. A comparison of our results to previously published demonstrates the efficiency of our approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124245175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 10 b 58 MHz CMOS A/D converter for high-speed video applications","authors":"Byeong-Lyeol Jeon, Kang-Jin Lee, Seunghoon Lee, Sang-Won Yoon","doi":"10.1109/ASPDAC.1999.759702","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759702","url":null,"abstract":"This paper describes a 10 b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 /spl mu/m CMOS show less than /spl plusmn/0.6 LSB and /spl plusmn/2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Timing-driven bipartitioning with replication using iterative quadratic programming","authors":"Shih-Lian T. Ou, Massoud Pedram","doi":"10.1109/ASPDAC.1999.759724","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759724","url":null,"abstract":"We present an algorithm for solving a general min-cut, two-way partitioning problem subject to timing constraints. The problem is formulated as a constrained programming problem and solved in two phases: cut-set minimization and timing satisfaction. A mathematical programming technique based on iterative quadratic programming (TPIQ) is used to find an approximate solution to the constrained problem. When the timing constraints are too strict to have a feasible solution, node replication is used to satisfy the constraints. Experimental results on the ISCAS89 benchmark suite show that TPIQ can solve the timing-driven bipartitioning problem with little impact on the chip size.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}