A 10 b 58 MHz CMOS A/D converter for high-speed video applications

Abstract

This paper describes a 10 b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 /spl mu/m CMOS show less than /spl plusmn/0.6 LSB and /spl plusmn/2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz.