用于高速数据通信的8b 52 MHz双通道CMOS A/D转换器

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.759701

Juhee Kim, Sungkil Hwang, Seunghoon Lee, Y. Jee

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引用次数: 1

摘要

本文介绍了一种用于综合业务数字网的8 b 52 MHz CMOS分频模数转换器。基于改进的时间交错结构的ADC消除了在传统双通道分频ADC中通常观察到的保持时间，以提高吞吐率。在0.8 /spl mu/m CMOS工艺下制作和测量的原型ADC在5 V和230 mW的8 b电平下的非线性小于/spl plusmn/0.4 LSB。

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An 8 b 52 MHz double-channel CMOS A/D converter for high-speed data communications

This paper describes an 8 b 52 MHz CMOS subranging analog-to-digital converter for Integrated Services Digital Network applications. The ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs for an increased throughput rate. The fabricated and measured prototype ADC in a 0.8 /spl mu/m CMOS process shows nonlinearities less than /spl plusmn/0.4 LSB at an 8 b level with 5 V and 230 mW.

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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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