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2003 8th International Symposium Plasma- and Process-Induced Damage.最新文献

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Process induced damage: what challenges lie ahead? 过程引起的损害:未来的挑战是什么?
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200912
T. Dao
{"title":"Process induced damage: what challenges lie ahead?","authors":"T. Dao","doi":"10.1109/PPID.2003.1200912","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200912","url":null,"abstract":"In the past few years, as the MOS transistor gate dielectric has become thinner - below 20 /spl Aring/ - there have been many questions regarding plasma and process induced damage (PID) effects on the thin gate oxide; such as \"There is no traditional gate oxide breakdown observed as the gate oxide becomes thinner, and hence no damage effect?\" Once the thin gate oxide quality and tunneling effects are understood, the gate oxide damage and PID effects have taken on new meanings. Meanwhile, question on the relevancy of PID lingers -\"Would PID still be a concern in future advanced semiconductor manufacturing?\" This paper presents a forward looking of advanced technology roadmaps - the implementation of strained silicon (SSi) on bulk or on insulator substrate, the advancement of fully depleted silicon-on-insulator (FDSOI) and double-gated structures, the planned introduction of high K gate stack, and the emerging of new memory technologies - and the projected implications on PID effects.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123779128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS downscaling and process induced damages CMOS缩尺和工艺引起的损伤
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199718
H. Iwai
{"title":"CMOS downscaling and process induced damages","authors":"H. Iwai","doi":"10.1109/PPID.2003.1199718","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199718","url":null,"abstract":"The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122547628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Systematic deprocessing: a technique for identification of the origins of process-induced damage and threshold voltage shifts 系统去处理:一种识别过程引起的损伤和阈值电压偏移的技术
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199724
A. Fischer, A. Krishnan, C. Kaneshige, Q. Hong, S. Krishnan
{"title":"Systematic deprocessing: a technique for identification of the origins of process-induced damage and threshold voltage shifts","authors":"A. Fischer, A. Krishnan, C. Kaneshige, Q. Hong, S. Krishnan","doi":"10.1109/PPID.2003.1199724","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199724","url":null,"abstract":"Back-end plasma process-induced damage has become a major concern for device reliability. Previous methods of process characterization do not allow for isolation of a single process within a metal loop. To solve this problem we developed a deprocessing technique that provides the capability for understanding the impact of a single process on transistor performance and reliability. This deprocessing technique is applied to pinpoint the source(s) of plasma damage. It is also used to identify the impact of backend plasma processes on interfacial Si-H concentration, which reportedly affects negative bias temperature instability lifetimes.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129375614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
P2ID 2002 industry survey of semiconductor process-induced damage p2id2002半导体制程损害产业调查
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200934
T. Hook, K. Eriguchi, T. Dao, S. Alba, P. K. Aum
{"title":"P2ID 2002 industry survey of semiconductor process-induced damage","authors":"T. Hook, K. Eriguchi, T. Dao, S. Alba, P. K. Aum","doi":"10.1109/PPID.2003.1200934","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200934","url":null,"abstract":"This is the first international semiconductor industry survey regarding PID (\"Process Induced Damage\") on semiconductor devices by P2ID. The purpose of P2ID is in understanding and managing PID issues faced by the semiconductor industry.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123531509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Charging damage during contact etch triggered by increased borderless nitride conductivity 无边界氮化物电导率增加引发接触蚀刻过程中的充电损伤
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199721
A. Cacciaot, A. Scarpa, S. Evseev, M. Diekema
{"title":"Charging damage during contact etch triggered by increased borderless nitride conductivity","authors":"A. Cacciaot, A. Scarpa, S. Evseev, M. Diekema","doi":"10.1109/PPID.2003.1199721","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199721","url":null,"abstract":"In this paper we evaluate the effect of nitride conduction on charging damage during contact etch. In particular, it is demonstrated that photoconduction is triggered in silicon nitride films when they are exposed to plasma during contact etch. As a consequence of this increased conductivity, they act as antennas, being able to collect charges from unstable plasmas and inject them into the gate oxide, thus causing charging damage.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116000858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interaction between ILD-process and metal-etch induced gate charging effect ild工艺与金属蚀刻诱导栅充电效应的相互作用
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199720
W. Lin, G. Sery
{"title":"Interaction between ILD-process and metal-etch induced gate charging effect","authors":"W. Lin, G. Sery","doi":"10.1109/PPID.2003.1199720","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199720","url":null,"abstract":"Interaction between ILD-process and metal-etch induced gate charging damage was investigated using via-intensive test structures and edge-intensive metal antenna structures. Strong interaction between the two effects was observed in multiple metal layer test structures. This interaction results in a marked turnaround behavior of the charging damage. This study also reveals that charging damage to gate oxide during via etch is dominated by the ILD deposition or etch process. This damage is independent of the number of vias but strongly depends on the relative position and the area of the metal holding the vias. The study also concludes that via-etch induced charging risk can be assessed by the metal area (to gate area) ratio rule DRC check at the layer of the metal holding the vias.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114880357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti process PECVD-Ti工艺对亚5nm栅极氧化物的等离子体损伤
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199722
H. Park, Jong Myeong Lee, Sang-Woo Lee, Jung‐Hun Seo, Kyoung Mo Koo, H. B. Lee, J. Jang, Dong Kyun Park, In-sun Park, G. Choi, U. Chung, J. Moon
{"title":"Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti process","authors":"H. Park, Jong Myeong Lee, Sang-Woo Lee, Jung‐Hun Seo, Kyoung Mo Koo, H. B. Lee, J. Jang, Dong Kyun Park, In-sun Park, G. Choi, U. Chung, J. Moon","doi":"10.1109/PPID.2003.1199722","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199722","url":null,"abstract":"Plasma-induced damage by the PECVD-Ti process on the leakage current of sub-5 nm gate oxide was investigated. The plasma conditions during the deposition of PECVD-Ti critically affected characteristics of the gate oxide such as the leakage current and the breakdown voltage. Lowering of plasma power in a deposition step improves the gate oxide properties but cannot clearly reduce all gate oxide failure. According to plasma damage monitoring analysis, a large plasma damage during the plasma ignition step was observed, which indicates that failure of the gate oxide was due to the unbalanced plasma ignition in the deposition step. It is very important to optimize process parameters and to control system conditions to prevent the unbalanced plasma ignition during the PECVD-Ti process.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129910366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) nitrided gate oxide 氟对三层(1.6/2.2/5.2 nm)氮化栅极氧化物先进CMOS工艺的影响
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200945
T. Hook, R. Kontra, J. Burnham, M. Lavoie
{"title":"The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) nitrided gate oxide","authors":"T. Hook, R. Kontra, J. Burnham, M. Lavoie","doi":"10.1109/PPID.2003.1200945","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200945","url":null,"abstract":"Fluorine is introduced into the PFET and NFET of a triple-oxide (1.6/2.2/5.2 nm) 90 nm nitrided-oxide CMOS technology. While the effects on the PFET gate oxide are relatively subtle, the NFET is very significantly affected. The effective thickness of the oxide increases by 0.5 nm, much of the nitrogen is removed, and the structural integrity of the film is compromised. Electrical data, SIMS, TEM, and HRTEM analysis are used to characterize the films.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of gate oxide quality as a function of downstream plasma exposure during flash memory fabrication 闪存制造过程中栅极氧化物质量与下游等离子体暴露关系的研究
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200931
S. Giancaterina, J. Rebrasse, B. Lecohier, O. Keller, M. Martinetti, S. Rounds
{"title":"Investigation of gate oxide quality as a function of downstream plasma exposure during flash memory fabrication","authors":"S. Giancaterina, J. Rebrasse, B. Lecohier, O. Keller, M. Martinetti, S. Rounds","doi":"10.1109/PPID.2003.1200931","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200931","url":null,"abstract":"Gate oxide is the most critical oxidation step in the flash memory fabrication sequence. Surfaces free of contaminants are required to grow high quality gate oxides. A correlation between oxide quality and resist removal techniques has been highlighted at the R8 STMicroelectronics production fab, comparing Axcelis FusionGemini ES asher results with those of full wet techniques.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of the process flow on negative-bias-temperature-instability 工艺流程对负偏置温度不稳定性的影响
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200943
A. Scarpa, L. van Marwijk, A. Cacciato, F. Ballarin
{"title":"Effect of the process flow on negative-bias-temperature-instability","authors":"A. Scarpa, L. van Marwijk, A. Cacciato, F. Ballarin","doi":"10.1109/PPID.2003.1200943","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200943","url":null,"abstract":"PMOSFET parametric degradation during negative-bias high temperature aging can depend on many steps of the manufacturing process flow. The effect of some process steps on NBTI is discussed with a phenomenological approach. In particular, we report a case in which plasma induced charging reduces the PMOSFET instability.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124473448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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