Process induced damage: what challenges lie ahead?

In the past few years, as the MOS transistor gate dielectric has become thinner - below 20 /spl Aring/ - there have been many questions regarding plasma and process induced damage (PID) effects on the thin gate oxide; such as "There is no traditional gate oxide breakdown observed as the gate oxide becomes thinner, and hence no damage effect?" Once the thin gate oxide quality and tunneling effects are understood, the gate oxide damage and PID effects have taken on new meanings. Meanwhile, question on the relevancy of PID lingers -"Would PID still be a concern in future advanced semiconductor manufacturing?" This paper presents a forward looking of advanced technology roadmaps - the implementation of strained silicon (SSi) on bulk or on insulator substrate, the advancement of fully depleted silicon-on-insulator (FDSOI) and double-gated structures, the planned introduction of high K gate stack, and the emerging of new memory technologies - and the projected implications on PID effects.