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2003 8th International Symposium Plasma- and Process-Induced Damage.最新文献

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Effects of gate notching profile defect on characteristic of cell NMOSFET in low-power SRAM device 栅极陷波缺陷对小功率SRAM器件中单元NMOSFET特性的影响
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200944
S. Seo, Sung-Jin Kim, Won-suk Yang, Jun-Yong Ju, Joo-Young Kim, S. Park, Seug-Gyu Kim, Ki-Joon Kim
{"title":"Effects of gate notching profile defect on characteristic of cell NMOSFET in low-power SRAM device","authors":"S. Seo, Sung-Jin Kim, Won-suk Yang, Jun-Yong Ju, Joo-Young Kim, S. Park, Seug-Gyu Kim, Ki-Joon Kim","doi":"10.1109/PPID.2003.1200944","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200944","url":null,"abstract":"The effects of gate notching profile defects on transistor performance in cell NMOSFETs of low-power SRAM devices with 0.12 /spl mu/m channel length were investigated. Experimentally, it was found that gate notching profile defects cause serious degradation of the transconductance and the transistor drive current. TSUPREM4 simulations showed that the degradation of transistor characteristics is related to the penetration of the gate notching into the channel region over the source/drain (S/D) extension region and the rapid reduction of gate electric field. Moreover, we found that the degradation of transistor performance is more sensitive to notch depth than notch height.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132545840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel wireless on-wafer plasma sensor using light-emitting diodes 一种利用发光二极体的无线晶圆等离子体感测器
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200950
N. Mise, T. Ono, T. Usui
{"title":"A novel wireless on-wafer plasma sensor using light-emitting diodes","authors":"N. Mise, T. Ono, T. Usui","doi":"10.1109/PPID.2003.1200950","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200950","url":null,"abstract":"We developed a novel wireless, on-wafer plasma sensor that uses light-emitting diodes (LEDs). This sensor measures the potential differences during plasma exposure that are a factor in charging damage occurring in semiconductor devices. The sensor's measurement principle is based on the diode characteristics and the measurement is very easy; we need only to expose the sensor to plasma and count the in-series LEDs that are bright. If they are bright, it means the applied voltage exceeds a known critical value. If they are dark, it means the voltage is below the value. Thus the sensor uses light for data acquisition, and no wire connections are necessary. Furthermore, it can be handled like a standard wafer. Its fundamentally quick and inexpensive measurement feature makes it highly advantageous for application to conventional measurements. This novel sensor makes it possible to measure plasma properties and minimize the potential of charging damage in real time.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129371974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NBTI in dual gate oxide PMOSFETs 双栅氧化pmosfet中的NBTI
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200942
P. Chaparala, D. Brisbin, J. Shibley
{"title":"NBTI in dual gate oxide PMOSFETs","authors":"P. Chaparala, D. Brisbin, J. Shibley","doi":"10.1109/PPID.2003.1200942","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200942","url":null,"abstract":"In advanced analog and mixed signal applications, Negative Bias Temperature Instability (NBTI) in dual gate oxide (DGO) technologies poses significant challenges for process development and robust analog circuit design. In this paper, Vt mismatch shift due to NBTI in a cascode current mirror is examined. The impact of stress time, temperature, gate voltage, drain voltage, and annealing on NBTI degradation is investigated over a wide range of stress conditions. Proper process trade-offs must be made to reduce NBTI degradation while integrating a DGO module into a high performance CMOS core process.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"43 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125756060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Reduction of plasma-radiation-induced interface states for plasma processes of charge-coupled-device image sensors using pulse-time-modulated plasma 利用脉冲时间调制等离子体降低电荷耦合器件图像传感器等离子体过程中等离子体辐射诱导的界面状态
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200946
N. Okigawa, Y. Ishikawa, S. Samukawa
{"title":"Reduction of plasma-radiation-induced interface states for plasma processes of charge-coupled-device image sensors using pulse-time-modulated plasma","authors":"N. Okigawa, Y. Ishikawa, S. Samukawa","doi":"10.1109/PPID.2003.1200946","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200946","url":null,"abstract":"We found that ultraviolet (UV) light from helium discharge plasmas and a metal halide lamp clearly induce SiO/sub 2/-Si interface states in a metal-silicon-nitride-oxide-silicon (MNOS) structure produced by charge-coupled-device (CCD) wafer processes. A dark current originating in the interface states of CCD image sensors also increases by this UV irradiation. Decreasing the UV light causes pulse-time-modulated (TM) plasma to suppress the interface states, resulting in a CCD dark current. Using optical filters, we revealed that a photon energy of 3.90 eV (318 nm) to 4.96 eV (250 nm) causes an increase in interface states. Even in a practical CCD process, we also found that TM plasma is more effective in suppressing interface states for micro-lens formation processes using CF/sub 4/ and O/sub 2/ plasma etching than CW plasma.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma damage reduction by using ISSG gate oxides 利用ISSG栅极氧化物降低等离子体损伤
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200916
G. Cellere, M. G. Valentini, M. Caminati, M. Vitali, A. Moro, A. Paccagnella
{"title":"Plasma damage reduction by using ISSG gate oxides","authors":"G. Cellere, M. G. Valentini, M. Caminati, M. Vitali, A. Moro, A. Paccagnella","doi":"10.1109/PPID.2003.1200916","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200916","url":null,"abstract":"Almost all processing steps involving the use of plasma can lead to gate oxide damage. Among these, damage due to inter metal dielectric (IMD) deposition has been of particular concern. At least two mechanisms can lead to gate oxide damage during this process step, that is non-conformal oxide coverage of exposed metal lines and photoemission due to UV photons generated inside the plasma. In particular, the gate oxide can be damaged even by very small tunneling currents, because it is weakened by the relatively high temperature used during IMD deposition. In this work, we have studied the damage induced during IMD deposition by using high density plasma (HDP) tools and different recipes for both the IMD and the gate oxide. In particular, we show that in situ steam generation (ISSG) gate oxides are by far more tolerant to plasma-induced damage than conventional ones. This assertion is demonstrated by using a damaging fluorinated silica glass (FSG) step, in conjunction with both conventional and ISSG gate oxides.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132845078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Process induced damages from various integrated circuit interconnection designs - limitations of antenna rule under practical integrated circuit layout practice 各种集成电路互连设计的过程损伤——天线规则在集成电路布置图实践中的局限性
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200948
J. Mercier, T. Dao, H. Flechner, B. Jean, D.B. Oscar, P. K. Aum
{"title":"Process induced damages from various integrated circuit interconnection designs - limitations of antenna rule under practical integrated circuit layout practice","authors":"J. Mercier, T. Dao, H. Flechner, B. Jean, D.B. Oscar, P. K. Aum","doi":"10.1109/PPID.2003.1200948","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200948","url":null,"abstract":"The accelerated process induced damage (PID) effect on MOS integrated circuit (IC) devices is observed depending on various IC interconnection line layout/design configurations related to non-gate transistor terminals - such as source, drain, well, and substrate. This phenomenon can occur even when the antenna sizes of the interconnection lines connected to each of the gate terminals (i.e. gate antennas) are small and meet the antenna rule. Without these various interconnection configurations to other terminals, no PID effect occurs. To analyze this phenomena in depth, a set of test structures is designed utilizing basic IC building block circuits - such as inverter, logic gates, registers and amplifiers - with small antennas connected to the specific circuit node(s) at various distances from each transistor. IC process induced charging is observed to activate transistors electrically and, hence, operates the circuits erratically. This phenomenon causes the accelerated PID effect. A set of selected examples of these test structures based on inverter circuits is presented. The test data show the accelerated PID effect on MOS transistors even with small gate antennas with a 5 0 to 1 antenna ratio.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128108022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Backend dielectric etch induced wafer arcing mechanism and solution 后端介质腐蚀诱导晶圆弧形成机理及解决方法
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200951
S. Ma, N. Hanabusa, B. Mays, S. Shoji, M. Kutney, T. Detrick, B. Patada, R. Straube
{"title":"Backend dielectric etch induced wafer arcing mechanism and solution","authors":"S. Ma, N. Hanabusa, B. Mays, S. Shoji, M. Kutney, T. Detrick, B. Patada, R. Straube","doi":"10.1109/PPID.2003.1200951","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200951","url":null,"abstract":"A significant challenge for dielectric etching in advanced chip designs is a new plasma damage phenomenon called \"wafer arcing.\" This randomly occurring problem is characterized by burned metal and \"worm-like\" arcing marks along the wafer's edge and the conducting wide metal lines around the die periphery. Arcing-induced particles also increase chamber contamination, requiring more maintenance and downtime. With the impact on yield per wafer, minimizing the frequency has become a key selection criterion for dielectric etch systems, especially for 300 mm manufacturing. Wafer arcing is a response to particular wafer surface structure conditions and plasma instability. Most conducive to this problem are dielectric etch process steps with a prior conductive layer beneath, such as pad and via etch. Arcing can be significantly reduced by a combination of cathode design to support better plasma stability, and electrostatic chuck and process kit design to minimize field gradients across the wafer. In addition, equipment operation parameter settings and process recipes can be optimized to reduce wafer arcing frequency. Providing an advanced chamber design has enabled us to achieve superior wafer arcing performance of less than 1 in 20,000 wafers.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134223746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution 等离子体损伤引起的栅极氧化降解与ILD帽氧化沉积有关——检测、定位和解决
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200927
S. Schulte, G. Dubois, D. Basso
{"title":"Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution","authors":"S. Schulte, G. Dubois, D. Basso","doi":"10.1109/PPID.2003.1200927","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200927","url":null,"abstract":"The article reports on the flow of detection, localization and resolution of a plasma damage related problem in a logic chip production line. The problem was observed on standard 0.25 /spl mu/m logic technology. The introduction and optimization of a voltage breakdown (VBD) test in ILT (in line test) routines led to the detection of an insufficient gate oxide quality. Using data-mining application software and taking into consideration the structure of the test routine, the root cause for the degradation of the gate-oxide was found to be ILD (inter-layer-dielectric) cap oxide deposition. A matrix design of experiment was used to optimize the plasma deposition process in order to minimize charging effects by paying attention to wafer uniformity and reproducibility. It is shown that the principal detractor for the quality of gate oxide was eliminated by introducing the new ILD cap oxide process.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma-induced charge damage and its effect on reliability in 0.115-/spl mu/m technology 等离子体诱导电荷损伤及其对0.115-/spl mu/m技术可靠性的影响
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200917
E. Li, D. Pachura, L. Duong, S. Prasad, D. Vijay
{"title":"Plasma-induced charge damage and its effect on reliability in 0.115-/spl mu/m technology","authors":"E. Li, D. Pachura, L. Duong, S. Prasad, D. Vijay","doi":"10.1109/PPID.2003.1200917","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200917","url":null,"abstract":"Plasma-induced damage on 0.115 /spl mu/m Cu dual damascene technology devices is investigated. The metal-via-metal structure shows more plasma damage than other metal structures. Plasma damage has little impact on NMOSFET hot carrier degradation. For PMOSFET NBTI degradation, the plasma damage on thick oxide is clearly observed.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134550736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield improvement by reducing charge-up damage of double polysilicon capacitors during via etch 通过减少双多晶硅电容器在经孔蚀刻过程中的充电损伤来提高产量
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200924
V. Beugin, M. Richard
{"title":"Yield improvement by reducing charge-up damage of double polysilicon capacitors during via etch","authors":"V. Beugin, M. Richard","doi":"10.1109/PPID.2003.1200924","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200924","url":null,"abstract":"The charge-up damage on polysilicon capacitors during via etch has been investigated in flash memory devices by varying aspect ratio, power, strip, surface ratio and etch process. A possible explanation of the damage is presented.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115428244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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