Process induced damages from various integrated circuit interconnection designs - limitations of antenna rule under practical integrated circuit layout practice

Abstract

The accelerated process induced damage (PID) effect on MOS integrated circuit (IC) devices is observed depending on various IC interconnection line layout/design configurations related to non-gate transistor terminals - such as source, drain, well, and substrate. This phenomenon can occur even when the antenna sizes of the interconnection lines connected to each of the gate terminals (i.e. gate antennas) are small and meet the antenna rule. Without these various interconnection configurations to other terminals, no PID effect occurs. To analyze this phenomena in depth, a set of test structures is designed utilizing basic IC building block circuits - such as inverter, logic gates, registers and amplifiers - with small antennas connected to the specific circuit node(s) at various distances from each transistor. IC process induced charging is observed to activate transistors electrically and, hence, operates the circuits erratically. This phenomenon causes the accelerated PID effect. A set of selected examples of these test structures based on inverter circuits is presented. The test data show the accelerated PID effect on MOS transistors even with small gate antennas with a 5 0 to 1 antenna ratio.