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2003 8th International Symposium Plasma- and Process-Induced Damage.最新文献

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Temperature effect on ultra thin SiO/sub 2/ time-dependent-dielectric-breakdown 超薄SiO/sub - 2/时间介电击穿的温度效应
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200941
K.P. Cheung
{"title":"Temperature effect on ultra thin SiO/sub 2/ time-dependent-dielectric-breakdown","authors":"K.P. Cheung","doi":"10.1109/PPID.2003.1200941","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200941","url":null,"abstract":"The unusually high temperature-acceleration factor and the non-Arrhenius behavior of ultra thin oxide can be explained by kinetic analysis using the physics-based kinetic model of oxide defect generation during electrical stress. The semi-quantitative treatment using known experimental value range is in good agreement with the reported data in the literature, lending strong support for the kinetic model. The estimated activation energy difference between thick and thin oxide relies on the fact that for thick oxide the hole current to electron current ratio is approximately constant. The resulting agreement with reported data lend support to the anode-hole-injection model (under high-field stress) unless the hydrogen release per injected electron happens to be of a similar order of magnitude.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Prediction of plasma charging damage during SiO/sub 2/ etching by VicAddress 用VicAddress预测SiO/ sub2 /蚀刻过程中的等离子体充电损伤
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200930
T. Yagisawa, T. Ohmori, T. Shimada, T. Makabe
{"title":"Prediction of plasma charging damage during SiO/sub 2/ etching by VicAddress","authors":"T. Yagisawa, T. Ohmori, T. Shimada, T. Makabe","doi":"10.1109/PPID.2003.1200930","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200930","url":null,"abstract":"We have proposed a prototype of plasma processing CAD, i.e. Vertically Integrated Computer Aided Design for Device processing (VicAddress), that numerically predicts dry etching and related charging damage to a future profile and nanometer scale lower-level elements in ULSI, as well as the low temperature plasma structure. VicAddress has been applied to investigate the dry etching of SiO/sub 2/ film, that requires ions with several hundred to a thousand of eV. Negative ion injection to a wafer was numerically predicted and designed in a pulsed two-frequency capacitively coupled plasma (2f-CCP) operated by a VHF (100 MHz) - LF (1 MHz) system. In this paper, we predict the velocity distribution incident on a wafer in a pulsed 2f-CCP by using a Monte Carlo method under the plasma structure given by RCT modeling. We discuss: functional separation of very high frequency sustaining and low frequency biasing sources; the negative charge injection mode to the SiO/sub 2/ wafer during etching; and control of excess-dissociation of CFj by high energy secondary electrons.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical characterization of ultrathin high k dielectrics 超薄高k介电体的物理特性
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200909
W. Vandervorst, B. Brijs, H. Bender, O. T. Conard, J. Pétry, O. Richard, S. Van Elshocht, A. Delabie, M. Caymax, S. De Gendt, V. Cosnier, M. Green, J. Chen
{"title":"Physical characterization of ultrathin high k dielectrics","authors":"W. Vandervorst, B. Brijs, H. Bender, O. T. Conard, J. Pétry, O. Richard, S. Van Elshocht, A. Delabie, M. Caymax, S. De Gendt, V. Cosnier, M. Green, J. Chen","doi":"10.1109/PPID.2003.1200909","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200909","url":null,"abstract":"Targeting very thin equivalent oxides (<1 nm) requires the deposition of (very) thin dielectrics onto silicon surfaces with minimal interfacial oxide. Typically, high-k dielectric layers are deposited using ALD or MOCVD with, at present, a prime emphasis on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Depending on the deposition conditions ALD as well as MOCVD show serious deficiencies in terms of film closure and material density for ultra thin (<3 nm) films. Various surface preparation methods and deposition conditions are used to improve the film quality.. Detailed studies on the film growth and its evolution requires the use of many analytical methods such as Rutherford backscattering spectrometry, low energy ion scattering, time-of-flight SIMS, (spectroscopic) ellipsometry and X-ray photoelectron spectroscopy. When trying to correlate the results in terms of film thickness, apparent discrepancies can be observed which relate to nonhomogeneous growth and reduced material density.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133709785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impacts of HF etching on ultra-thin core gate oxide integrity in dual gate oxide CMOS technology 双栅氧化物CMOS技术中HF刻蚀对超薄芯栅氧化物完整性的影响
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200921
Da-Yuan Lee, Horng-Chih Lin, C. Chen, Tiao-Yuan Huang, Tahui Wang, Tze-Liang Lee, Shih-Chang Chen, M. Liang
{"title":"Impacts of HF etching on ultra-thin core gate oxide integrity in dual gate oxide CMOS technology","authors":"Da-Yuan Lee, Horng-Chih Lin, C. Chen, Tiao-Yuan Huang, Tahui Wang, Tze-Liang Lee, Shih-Chang Chen, M. Liang","doi":"10.1109/PPID.2003.1200921","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200921","url":null,"abstract":"In this paper, we investigate the effects of HF etching on the integrity of ultra-thin oxides in dual gate oxide (DGO) CMOS technologies. We found that both the HF concentration in the etching solution and the over etching (OE) time are important parameters that greatly affect the device performance and reliability. Our results indicate that, with a proper over etching period, using a concentrated HF solution results in better ultra-thin gate oxides in terms of reduced defect density, improved device performance and reliability, compared to using diluted HF solution. It is also found for the first time that negative-bias-temperature instability (NBTI) immunity for PMOSFETs is improved by using concentrated HF solutions.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133009561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Initial gate leakage in ultra thin SiO/sub 2/ - the role of a brief stress 初始栅漏在超薄SiO/ sub2 /中-短暂应力的作用
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200938
K.P. Cheung
{"title":"Initial gate leakage in ultra thin SiO/sub 2/ - the role of a brief stress","authors":"K.P. Cheung","doi":"10.1109/PPID.2003.1200938","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200938","url":null,"abstract":"For ultra thin oxide, the preferred plasma charging damage detection method has been narrowed down to initial gate leakage. The initial gate leakage measurement can in principle distinguish stress-induced-leakage-current (SILC) from soft breakdown if the test device is small. In a previous report, we showed that the expected sharp distinction between broken devices and non-broken devices does not exist when several devices are measured for very thin oxide. Here, the explanation for the lack of sharp distinction between broken and non-broken devices is provided with the support of new data. It is clear that there is a basic difference between plasma charging stress and bench-top electrical stress of ultra thin oxide. The results indicate that, to obtain a better measure of plasma charging damage using gate leakage, a brief stress is necessary.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125498365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Metal gate and high-k integration for advanced CMOS devices 先进CMOS器件的金属栅极和高k集成
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200913
B. Guillaumot, X. Garros, F. Lime, K. Oshima, J. Chroboczek, P. Masson, R. Truche, A. Papon, F. Martin, J. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. Autran, T. Skotnicki, S. Deleonibus
{"title":"Metal gate and high-k integration for advanced CMOS devices","authors":"B. Guillaumot, X. Garros, F. Lime, K. Oshima, J. Chroboczek, P. Masson, R. Truche, A. Papon, F. Martin, J. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. Autran, T. Skotnicki, S. Deleonibus","doi":"10.1109/PPID.2003.1200913","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200913","url":null,"abstract":"An advanced CMOS process has been proposed which include key features : 75 nm gate length, damascene metal gate, high-k dielectrics with 1.35 nm equivalent oxide thickness (EOT). Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface Low gate current and low subthreshold slope make it attractive for low stand by power application.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130155360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Plasma-induced charging in two bit per cell SONOS memories 等离子体诱导充电在每单元2位SONOS存储器
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200914
Y. Roizin, M. Gutman, R. Yosefi, S. Alfassi, E. Aloni
{"title":"Plasma-induced charging in two bit per cell SONOS memories","authors":"Y. Roizin, M. Gutman, R. Yosefi, S. Alfassi, E. Aloni","doi":"10.1109/PPID.2003.1200914","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200914","url":null,"abstract":"Plasma induced charging in oxide-nitride-oxide (ONO) stacks and its influence on device and reliability performance were investigated on microFlash/spl reg/ two bit per cell memory devices. Experimental data indicate that UV radiation combined with the voltage built-up at the electrodes is the main cause of the observed Vt increase. Charging effects are more pronounced for scaled down devices with narrow word lines. An enhanced narrow channel effect is shown to be related to negative charges trapped in the nitride of ONO at the edges of the memory cell. Charging leads to the degradation of retention properties and results in the increased Vt spread. To decrease ONO charging a complex of measures was implemented that included screening of problematic equipment, development of special protecting circuits and improvement of the device design.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Recent trends in 300-mm plasma equipment 300毫米等离子体设备的最新趋势
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200949
G. Vinogradov
{"title":"Recent trends in 300-mm plasma equipment","authors":"G. Vinogradov","doi":"10.1109/PPID.2003.1200949","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200949","url":null,"abstract":"The main development trends of 300-mm plasma equipment, particularly etchers, are further increasing competition between capacitive and inductive plasma sources. Capacitive plasma sources increase excitation frequency in order to attain low-pressure high-density plasma conditions, while inductive sources essentially shrink the discharge gap and cover the low gas residence time range previously occupied exclusively by their capacitive counterparts. Both systems seem to be converging at the very limit for advanced oxide etchers. Wide-gap inductive sources are successfully replacing capacitive systems in polysilicon and metal etch. Microwave systems are still in the minority and will fail to occupy a noticeable place in the 300-mm market in the near future.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124633788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comprehending scaling effects on plasma damage 理解等离子体损伤的尺度效应
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1199723
A. Krishnan, S. Krishnan
{"title":"Comprehending scaling effects on plasma damage","authors":"A. Krishnan, S. Krishnan","doi":"10.1109/PPID.2003.1199723","DOIUrl":"https://doi.org/10.1109/PPID.2003.1199723","url":null,"abstract":"The dependence of the gate oxide current (during plasma processes) on the antenna ratio determines the significance of plasma damage for the product. This relationship is shown to be linear in the plasma-current limited regime and sub-linear in the plasma-voltage limited regime. The implication of this sub-linear dependence is that the fail fraction at high antenna ratio is not a reliable indicator of susceptibility to charging damage, and a complete model incorporating plasma and oxide current-voltage characteristics is necessary for accurate assessment of charging damage.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133871508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ion orbits in electron shading damage 电子遮蔽损伤中的离子轨道
2003 8th International Symposium Plasma- and Process-Induced Damage. Pub Date : 2003-04-24 DOI: 10.1109/PPID.2003.1200926
T. Madziwa-Nussinov, D. Arnush, F.F. Chen
{"title":"Ion orbits in electron shading damage","authors":"T. Madziwa-Nussinov, D. Arnush, F.F. Chen","doi":"10.1109/PPID.2003.1200926","DOIUrl":"https://doi.org/10.1109/PPID.2003.1200926","url":null,"abstract":"In Hashimoto's' hypothetical mechanism for electron shading damage, the photoresist at the tops of trenches and vias collects a negative charge from the thermal electrons, creating an electric field (E-field) which prevents electrons from reaching the trench bottom, where a \"collector\" is located. The ions, accelerated by the sheath electric field, are driven straight into the trench and impinge on the collector, charging it positive if it is isolated. The electric fields inside the trench can also deflect the ions into the sidewalls, causing notching and other deformations of the etch profile The present effort aims to test the hypothesis by scaling the submicron features to macroscopic size so that the currents and potentials inside the trench can be measured and compared with computations. This paper concerns the theoretical part of the work; namely, self-consistent computations of the E-fields and ion orbits inside the trenches.","PeriodicalId":196923,"journal":{"name":"2003 8th International Symposium Plasma- and Process-Induced Damage.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123555248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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