CMOS downscaling and process induced damages

Abstract

The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.