56th Electronic Components and Technology Conference 2006最新文献

{"title":"Optical high speed symmetric multi-processor link implementation","authors":"D. Kuchta, C. Baks, E. Mintarno, D. de Araujo, M. Cases","doi":"10.1109/ECTC.2006.1645866","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645866","url":null,"abstract":"High-end computing servers configured as symmetric multi-processor (SMP) systems rely on parallel high speed links for interconnection between the processors. With each new generation of processor, the bandwidth of the SMP link is increased. Wired copper cables are still the technology of choice for this application but with each increment in bandwidth, fiber optic interconnects become more competitive solution contenders. To obtain an early look at the issues facing fiber optics in the SMP application, two types of optical links, all-optical and hybrid-optical, were built and characterized in a real system. These links were evaluated in terms of cost, size, power dissipation, temperature rise, electrical interface, latency and bit error ratio (BER). In both implementations, an 8-way SMP system was successfully operated","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121311728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wire and via modeling and simulation solutions for a tri-grid mesh plane ceramic packaging","authors":"Zhaoqing Chen, D. Becker, G. Katopis","doi":"10.1109/ECTC.2006.1645818","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645818","url":null,"abstract":"To accurately evaluate interconnect net electrical properties of the tri-grid structure we need to model the wires and vias in this structure. Due to the high application frequencies and the non-TEM nature of the propagating mode in this structure, the use of full-wave electromagnetic tools is necessary. In this paper we describe the principles and results of three different modeling and simulation solutions. The modeling and simulation solutions are based on full-wave electromagnetic simulations on short physical structure sections. The solutions can be applied to the transient circuit simulation on longer interconnect nets for evaluating system reflection, transmission, near end noise, and far end noise. The comparison shows the per-unit-length RLGC is the most efficient model and simulation method for this application","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114234742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding","authors":"N. Tanaka, Y. Yoshimura, T. Naito, C. Miyazaki, T. Uematsu, K. Hanada, N. Toma, T. Akazawa","doi":"10.1109/ECTC.2006.1645751","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645751","url":null,"abstract":"To verify the operation of three-dimensional SiP with through-hole electrode interconnections, we manufactured a prototype of a 3D-SiP sample composed of a MCU, an interposer, and a synchronous DRAM (SDRAM) chip using a proposed mechanical caulking operation. A new electrode design of LSI for through-hole electrode interconnection is important for establishing a stable mass-production process. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and characterization of thin film broadband resistors on LCP for RF applications","authors":"S. Horst, S. Bhattacharya, S. Johnston, M. Tentzeris, J. Papapolymerou","doi":"10.1109/ECTC.2006.1645895","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645895","url":null,"abstract":"Resistors have several applications in high frequency circuits including uses in attenuators, terminations, and power dividers among others. To date, there has been very little attempt to characterize embedded resistor performance on organics above 18 GHz. In this paper, RF measurements of embedded thin film resistors up to 40 GHz are presented on a liquid crystal polymer (LCP) substrate using a commercially available laminated foil to form the thin film NiCrAlSi resistors. Measurements have been demonstrated to be accurate to 5% of their simulated values across the frequency band","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121357374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature- and moisture-induced warpages of COG package with non-conductive paste adhesive","authors":"M. Tsai, C. Huang, C. Chiang, W. Chen, S. Yang","doi":"10.1109/ECTC.2006.1645925","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645925","url":null,"abstract":"The use of non-conductive paste (NCP) or film (NCF) adhesives to replace the ACF (anisotropic conductive film) in COG (chip on glass) packages may be a possible solution for the low cost and finer bump pitch application to the LCDs (liquid crystal displays). However, when the NCP is applied, reliability issues, such as excessive warpage, interfacial delamination, and increasing contact resistance of bumps, occur in the COG packages. The goal of this paper is to experimentally and numerically study the warpage of NCP-bonded COG packages with and without fillet after cured in the chamber with 150degC for 2 hrs, under thermal and moisture loads. Twyman-Green interferometry is used for measuring the warpages (out-of-plane deformations) of the COG packages due to such loads. Three-dimensional finite element method (FEM) is used for calculating the warpage and the results are compared with experimental observations in order to provide an insight to it in terms of mechanics. The full-field out-of-plane deformations (warpage) of the COG packages with and without fillet have been experimentally measured under thermal cycling and moisture loading. The results show that, right after manufacturing, the much apparently concave-up-shape warpages are found at the COG packages with fillet, but slightly concave-down shapes for those without fillet. And the warpages decrease with the heating temperature increasing. The warpages (fringe patterns) of the COG package, determined from experiment and FEM, are quite consistent for case with fillet or without fillet. Prior to investigating the moisture effect on warpages of the COG packages, the moisture-induced strain of the NCP at the condition of 29degC /85%RH for 12 hrs has been obtained to be epsivm = 0.3 % by testing NCP/silicon bi-material plate with a combination of Twyman-Green experiment and Timoshenko's bi-material theory. This strain value has been incorporated into the FEM analysis, and the obtained warpage distributions of COG packages with and without fillet are compared with those from Twyman-Green experiment. It is shown that moisture-absorption expansion strain leads to dramatically reduce the warpage of the COG package with fillet, but not for that without fillet","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126982744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Sn grain size and orientation on the thermomechanical response and reliability of Pb-free solder joints","authors":"T. Bieler, H. Jiang, L. Lehman, T. Kirkpatrick, E. Cotts","doi":"10.1109/ECTC.2006.1645849","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645849","url":null,"abstract":"The size and orientation of Sn grains in Pb-free, near eutectic SAC solder joints were examined. A clear dependence of the thermomechanical response of these solder joints on Sn grain orientation was observed. Solder balls with Sn grains of particular orientation (a-axis perpendicular to the substrate) were observed to fail before neighboring balls with different orientations. This results from the fact that the coefficient of thermal expansion of Sn along the a-axis is half the value along the c-axis; joints observed to be damaged had maximum mismatch in the coefficient of thermal expansion between solder and substrate at the joint interface, as well as tensile stress modes during the hot part of the cycle","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127606485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Photolithography on three dimensional substrates","authors":"P. Ivey, R. McWilliam, A. Maiden, G. Williams, A. Purvis, L. Seed","doi":"10.1109/ECTC.2006.1645660","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645660","url":null,"abstract":"Photolithography is the primary technique for patterning planar substrates. However, some higher-density packaging solutions require tine features to be patterned onto grossly non-planar substrates, for example, in mechanical, optical and fluidic microsystems and packaging schemes. Standard photolithography cannot be used in these cases because the inevitable gap between the (planar) mask and (non-planar) substrate causes diffractive line broadening and loss of resolution. We address this issue by realising the mask as a computer generated hologram (CGH), which can then be illuminated to generate an image in space corresponding to the required non-planar profile. The CGHs are derived from analytical expressions and encode both amplitude and phase information. We illustrate the performance with a 100 mum line exposed onto a substrate in the form of a plane/slope/plane, in which the change in depth is 40mm. Enhancements to the line shape are discussed that make the technique more robust to manufacturing process variations. The fact that features in the range 10-100 mum can be imaged at large distance whilst coping with significant changes of depth indicates that the technique shows great potential in the microelectronics packaging industry","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromigration lifetime statistics for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages","authors":"Seung-Hyun Chae, Xuefeng Zhang, H. Chao, K. Lu, P. Ho, Min Ding, P. Su, T. Uehling, L. Ramanathan","doi":"10.1109/ECTC.2006.1645719","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645719","url":null,"abstract":"A series of electromigration tests were performed as a function of temperature and current density to investigate lifetime statistics for Pb-free solder with Cu or Ni under-bump-metallization (UBM). Based on the overall shape of resistance traces, a conservative failure criterion for time-to-failure was defined and the results were compared with those based on the conventional open-failure criterion. Solder joints with Cu UBM had a longer lifetime than with Ni UBM, based on the open-failure criterion; however, the lifetime with Ni UBM became comparable when the conservative criterion was applied. The Joule heating effect was accounted for based on experiments and finite element analysis. The temperature of solder joints was determined to be approximately 15degC higher than that at the Si die surface when 1 A of current was passed. For solder with Cu UBM, voids formed initially at the Cu6Sn 5/solder interface while the final open failure occurred at the Cu3Sn/Cu6Sn5 interface. For Ni UBM, voids formed initially at the Ni3Sn4/solder interface leading to failure at the Ni3Sn4/solder interface","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"44 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Edge viewing photodetectors for strictly in-plane lightwave circuit integration and flexible optical interconnects","authors":"D. Guidotti, Jianjun Yu, M. Blaser, V. Grundlehner, G. Chang","doi":"10.1109/ECTC.2006.1645746","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645746","url":null,"abstract":"We have developed a parallel process for the cost effective fabrication of active lightwave circuits and optical transceivers. In this novel process no out-of-plane beam turning components (mirrors or lenses) are used and light never leaves the waveguide except at the photodetector","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132732564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interface failure in lead free solder joints","authors":"R. Darveaux, C. Reichman, N. Islam","doi":"10.1109/ECTC.2006.1645763","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645763","url":null,"abstract":"The phenomenon of interface failure in lead free solder joints was explored using solder joint array tensile testing. The effects of pad metallization, solder alloy, reflow conditions, and post reflow thermal aging were quantified. The joint strength ranged from 5 to 115MPa. The joint ductility dropped to zero in some cases. The interface microstructure and failure mode were characterized for each combination of factors. Most of the trends were linked to microstructural features of the interface. A ductile-to-brittle transition strain rate (DTBTSR) was defined as a metric to quantify the performance of a specific joint relative to interface failure. The DTBTSR ranged from 10-3 /sec to 10/sec for the conditions studied","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}