56th Electronic Components and Technology Conference 2006最新文献_第10页

Implementation of a W-CDMA direct-conversion IQ modulator module including evaluation of chip-package-board interactions 一种W-CDMA直接转换IQ调制器模组的实现，包括评估晶片封装板的相互作用

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645891

F. Han, J. Wu, T. Horng, J. Lin, C.C. Tu

引用次数: 0

Interfacial strength assessment of Cu-epoxy system by atomic force microscope 用原子力显微镜评价cu -环氧体系的界面强度

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645692

C. Wong, E. V. Kuznetsov, Bing Xu, M. Yuen

引用次数: 0

Synchrotron radiation based X-ray micro-diffraction study on reliability issues of solder joints in electronic packaging technology 基于同步辐射的x射线微衍射研究电子封装工艺中焊点的可靠性问题

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645924

J. Suh, J. Nah, K. Tu, N. Tamura

引用次数: 0

Improving mold compound adhesion to Ni/Pd/Au pre-plated lead frames 提高模具复合材料对Ni/Pd/Au预镀引线框架的附着力

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645845

G. Kim, James Hurley, A. Dhoble, S. Avdić

{"title":"Improving mold compound adhesion to Ni/Pd/Au pre-plated lead frames","authors":"G. Kim, James Hurley, A. Dhoble, S. Avdić","doi":"10.1109/ECTC.2006.1645845","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645845","url":null,"abstract":"A unique approach for investigating new epoxy mold compounds with improved adhesion to Ni/Pd/Au leadframes is described. This approach consists of three parts: 1) the calculation of polar gammap and dispersive gammad surface free energy components of various model epoxy mold compounds and Ni/Pd/Au-plated leadframes, respectively, derived from dynamic contact angle measurements at room temperature using water and diiodomethane, 2) interpretation of the results in terms of the geometric mean theory of Owens, Wendt, Rabel and Kaelble, which includes the construction of the wetting envelope for the Ni/Pd/Au leadframe under various environmental conditions, and 3) a measurement technique for the true contact angle thetas and hence the thermodynamic work of adhesion Wa according to the Young-Dupre equation compared to actual adhesion. The calculated thermodynamic work of adhesion was compared to actual adhesion values obtained using a modified die shear adhesion test. Reasonable correlation was obtained between the two tests, allowing the contact angle measurement to be adapted as a rapid screening tool for identifying promising leadframe and EMC material candidates. Actual epoxy molding compounds are formulated based on information from the wetting angle experiments and die-shear adhesion tests of unfilled model compounds. Fully-formulated epoxy molding compounds are characterized using traditional tab-pull adhesion tests (Ju et al., 2004) and thermal cycle reliability tests on actual leaded packages. Further results from the surface energies, the resulting adhesion strengths, and the interfacial shear stresses between the EMC and the leadframe are discussed","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"63 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121953737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Fabrication and assembly of a novel high-efficiency UHF RFID tag on flexible LCP substrate 柔性LCP基板上高效率超高频射频标签的制造与组装

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645832

S. Basat, S. Bhattacharya, A. Rida, S. Johnston, L. Yang, M. Tentzeris, J. Laskar

引用次数: 34

Materials effects on reliability of FC-PBGA packages for Cu/low-k chips 材料对Cu/低钾芯片FC-PBGA封装可靠性的影响

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645869

Li Li, J. Xue, M. Ahmad, M. Brillhart, Min Ding, G. Lu, P. Ho

{"title":"Materials effects on reliability of FC-PBGA packages for Cu/low-k chips","authors":"Li Li, J. Xue, M. Ahmad, M. Brillhart, Min Ding, G. Lu, P. Ho","doi":"10.1109/ECTC.2006.1645869","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645869","url":null,"abstract":"Reliability of the flip-chip plastic ball grid array (FC-PBGA) packages is highly dependent on the properties of the constituent components and the interface formed between them. The relative mechanical compliances and thermal mismatch between the silicon chip, the underfill material and the organic laminate substrate are particularly important to the design and performance the package. Strong coupling between the chip and the substrate can cause chip cracking, delamination of interlayer dielectrics (ILD), delamination of underfill and problems associated with BGA interconnection when the package is assembled to a printed circuit board (PCB). The problem became more severe as we migrate to the 90nm and 65nm silicon technology nodes where low-k ILD is widely used. Combined experimental and modeling methods were used to investigate the thermo-mechanical behavior and failure mechanisms controlling FC-PBGA package reliability. Materials effect of new generation of underfill materials was first studied for minimizing the chip-substrate thermo-mechanical coupling. Fully assembled FC-PBGA packages with various underfill materials were evaluated following a carefully designed analysis and screening flow. Thermo-mechanical response of the package was measured and analyzed using high resolution moire interferometry and numerical modeling techniques. Four-point bending test was also used to characterize interfacial fracture energy for the critical interface between die passivation and underfill material. The experiments and modeling were correlated with the JEDEC standard component-level reliability testing results. The combined experimental and numerical analysis confirmed our selection of the substrate, underfill and other package materials and demonstrated that significantly improved reliability of the flip-chip PBGA packages can be achieved by controlling thermo-mechanical coupling of the silicon die and the package, and by controlling various important interfaces within the package","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121684552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications 铜互连用于高性能和细间距倒装芯片数字应用和超小型射频模块应用

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645632

R. Tummala, P. Markondeya Raj, A. Aggarwal, G. Mehrotra, S. Koh, S. Bansal, Tan Teck Tiong, C. Ong, J. Chew, K. Vaidyanathan, V. Srinivasa Rao

引用次数: 34

Wafer thinning solution for wafer-level-capped MEMS devices 晶圆级封顶MEMS器件的晶圆减薄解决方案

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645793

E. Lacsamana, M. Mena, R. Navarro, N. Kuan, T. R. Spooner

引用次数: 0

Fluxless bondings of silicon to alumina substrate using electroplated eutectic Au-Sn solder 使用电镀共晶金锡焊料的硅与氧化铝衬底的无焊剂结合

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645913

J.S. Kim, W. Choi, A. Shkel, C.C. Lee

{"title":"Fluxless bondings of silicon to alumina substrate using electroplated eutectic Au-Sn solder","authors":"J.S. Kim, W. Choi, A. Shkel, C.C. Lee","doi":"10.1109/ECTC.2006.1645913","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645913","url":null,"abstract":"Large 6 mm times 9 mm silicon dice have been successfully bonded on alumina substrate with electroplated Au80Sn20 eutectic alloy. Eutectic AuSn is one of the best known hard solders having excellent fatigue-resistance and mechanical properties. A fluxless bonding process in 50 militorrs of vacuum environment is presented. Vacuum environment is employed to prevent tin oxidation during the process. The oxygen content is expected to be reduced by a factor of 15,200, comparing to bonding in air. One of the challenges in silicon-to-alumina bonding is the large mismatch in thermal expansion between silicon of 2.7 times 10-6 ppm/degC and alumina of 7 times 10 -6 ppm/degC. Electroplating method is used to build multi-layer solder. It is an economical alternative to vacuum deposition method and can produce thick solders. Joints fabricated are examined using scanning electron microscope (SEM), and energy dispersive X-ray spectroscopy (EDX). It is found that proper bonding condition is needed to turn the stacked layers into a uniform AuSn eutectic alloy. Nearly void-free joints are achieved and confirmed by a scanning acoustic microscope (SAM). To evaluate the reliability of the solder joint and the bonded structure, samples go through thermal cycling test to determine failure modes. Microstructure changes of the solder joints during thermal cycling test are also investigated","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122165291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Systematic evaluation of die thinning application in a power SIPs by simulation 通过仿真系统评价了模具减薄在功率SIPs中的应用

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645773

Y. Liu, D. Desbiens, S. Irving, T. Luk, C. Lolar, Yumin Liu, Qiuxiao Qian

{"title":"Systematic evaluation of die thinning application in a power SIPs by simulation","authors":"Y. Liu, D. Desbiens, S. Irving, T. Luk, C. Lolar, Yumin Liu, Qiuxiao Qian","doi":"10.1109/ECTC.2006.1645773","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645773","url":null,"abstract":"In this paper, a lead frame based system in package (SIP) for power management is examined. This package is built using multiple die types including power IGBTs, diodes, and IC controllers. To maximize product performance the power components use an ultra thin back grind. Thin dies minimize RDS(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. However, the ultra thin die could be a potential risk for die cracking if it is done without careful evaluation, especially for die thickness as thin as 90 mum and 50 mum. So it is critical to understand the impact of thinning dies on the reliability of the product in assembly manufacture and vary reliability tests. Modeling and simulation with a smaller amount of empirical testing is a good way to evaluate this thin die application quickly and at a lower cost. Therefore, the objective of this paper is to fully investigate the thin die application in a power SIP with systematic simulation and analysis before real application. A large complicated and advanced 3D FEA model framework is developed for the SIP. The major modeling and evaluation work is categorized into two areas: One is to check the impact of the thin die on different assembly processes. The other is to simulate the major reliability tests such as temperature cycle (TMCL) and component-level reflow process. Comprehensive evaluation and analysis of the modeling and simulation results for the thin die application to a Fairchild power SIP are presented","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131368896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12