56th Electronic Components and Technology Conference 2006最新文献

{"title":"Development and characterization of large silicon microchannel heat sink packages for thermal management of high power microelectronics modules","authors":"Hengyun Zhang, Qingxin Zhang, S. Chong, Damaruganath Pinjala, Xiaoping Liu, P. Chan","doi":"10.1109/ECTC.2006.1645778","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645778","url":null,"abstract":"In this paper, the development of large-sized silicon microchannel heat sink (SMHS) packages for high power dissipation microelectronic modules is presented. The microchannel wafer was designed and fabricated through deep reactive ion etching on the 8\" (100) wafer, which included 500 microchannels arranged in parallel and each channel possessed a depth of 400mum. The channel wafer was then bonded to a cover wafer to form the closed flow channel. Two wafer bonding techniques, gold diffusion bonding and bis-benzocyclobutene (BCB) bonding were evaluated. Large thermo-mechanical stress was induced in the first technique, which may not be suitable for the large silicon wafer bonding. In the second technique, a BCB bonding process was successfully developed by producing a bonding layer of around 5mum of minimal stress and free from micro voids. Fluidic interconnects were formulated through the use of elastic room-temperature vulcanizing silicone material between the cover wafer and the metallic housing to minimize the bonding stress. Both hydraulic tests and thermal modeling were conducted for the fabricated SMHS packages. All the heat sink packages with BCB bonding passed hydraulic tests at around 60 psi at a flowrate of 4 l/min, whereas those with gold diffusion bonding were found to fail at a pressure of 20-30 psi. The workability of the SMHS package for thermal management of high power microelectronics modules is demonstrated through a thermal model","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"572 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Health monitoring for damage initiation & progression during mechanical shock in electronic assemblies","authors":"P. Lall, P. Choudhary, S. Gupte, J. Suhling","doi":"10.1109/ECTC.2006.1645630","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645630","url":null,"abstract":"Electronic products may be subjected shock and vibration during shipping, normal usage and accidental drop. High-strain rate transient bending produced by such loads may result in failure of fine-pitch electronics. Current experimental techniques rely on electrical resistance for determination of failure. Significant advantage can be gained by prior knowledge of impending failure for applications where the consequences of system failure may be catastrophic. This research effort focuses on an alternate approach to damage-quantification in electronic assemblies subjected to shock and vibration, without testing for electrical continuity. The proposed approach can be extended to monitor product-level damage. In this paper, statistical pattern recognition and leading indicators of shock-damage have been used to study the damage initiation and progression in shock and drop of electronic assemblies. Statistical pattern recognition is currently being employed in a variety of engineering and scientific disciplines such as biology, psychology, medicine, marketing, artificial intelligence, computer vision and remote sensing based in Jain, et. al. (2000). The application quantification of shock damage in electronic assemblies is new. Previously, free vibration of rectangular plates has been studied by various researchers as presented in Leissa (1969), Young (1950), Gorman (1982), Gurgoze (1984), and Wu (2003) for development of analytical closed-form models. In this paper, closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response has been quantified. A damage index for experimental damage monitoring has been developed using the failure indicators. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any electronic assembly structure irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression can not be monitored. Hence the proposed method does not require the assumption that the failure occurs abruptly after some number of drops and can be extended to product level drops","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115303091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A MEMS-based compliant interconnect for ultra-fine-pitch wafer level packaging","authors":"E. Liao, A. Tay, S. Ang, H. Feng, R. Nagarajan, V. Kripesh, R. Kumar, M. Iyer","doi":"10.1109/ECTC.2006.1645812","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645812","url":null,"abstract":"A novel compliant flip-chip interconnect in the form of a planar microspring is presented in this paper. Different spring geometries are evaluated and compared in terms of compliances and electrical parasitics. It is shown that the J-shape spring design gives a better balanced performance. Further numerical studies reveal the geometric dependence of the compliances of J-shape spring interconnects, and also the influence of the sacrificial material upon the electrical performance of the interconnects. The wafer-level process flow for fabrication of the planar microspring interconnects is described and discussed. Prototype interconnects are fabricated by combining planar technology and 3D surface micromachining technology","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115490263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System-on-packaging with electro-absorption modulator for 60 GHz band radio-over-fiber link","authors":"K. Choi, Yong‐Duck Chung, Dong-Suk Jim, Y. Kang, Byoung-Tae Ahn, Kyoung-Ik Cho, J. Moon, Jeha Kim","doi":"10.1109/ECTC.2006.1645863","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645863","url":null,"abstract":"We developed a system-on-packaging (SoP) with an electro-absorption modulator (EAM) for a 60 GHz band radio-over-fiber (RoF) link. It consists of an EAM device, a microstrip filter, and a low noise amplifier (LNA). The microstrip filter was used to achieve the impedance matching between the EAM device and the LNA and to reject the local oscillator (LO) frequency of the heterodyne system. The frequency response and the effect of the EAM bias voltage of a simple RF/optical link were measured. A 60 GHz band RoF link with 2.4 GHz intermediate frequency (IF) was prepared to measure the transmission characteristics of 16 QAM data","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"424 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assembly technology development for 3D silicon stacked module for handheld products","authors":"V. Ganesh, S. Lim, D. Witarsa, H. W. Yin, M. Kumar, L. A. Lim, S. Yoon, V. Kripesh","doi":"10.1109/ECTC.2006.1645822","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645822","url":null,"abstract":"The objective of this consortium research work is to develop a 3D SiP based on silicon platform technology for integrating heterogeneous multifunctional devices for handheld products with imaging application. The developed 3D SiP can be used for signal speed of 2Gbps with designed silicon through via structures and matched transmission lines. The thermal performance of the 3D SiP is optimized for 3 watts heat dissipation by natural convection cooling. This paper focuses on the process development of five key assembly technologies used to fabricate the 3D silicon carrier SiP. The five key assembly technologies are: (1) wafer thinning, (2) thin flip chip attach on silicon carrier, (3) ultra low loop wire bonding (4), glass cap fabrication and sealing and (5) carrier stacking. The developed SiP has 3 silicon carriers with 4 flip chip and 1 wire bond die chip attached to them and the carrier is stacked one above the other to form the 3D silicon carrier SiP. Key developments in the five assembly technologies include 8\" bumped wafer thinning to 100mum, lower flip chip interconnect height between the chip and the carrier down to 35mum, 40 to 50mum low loop wire bonding on overhang by direct reverse wire bonding method using 1 mil diameter Au wire, investigation of 3 types of thin film metallization for wedge bonding, investigation of two different methods in fabricating glass cap 1, Si-anodic bond glass cap 2, SiUV adhesive bond glass cap and investigation on different types of adhesives for cap sealing","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel lead free nanoscale nonconductive adhesive (NCA) for ultra-fine pitch interconnect applications","authors":"Yi Li, K. Moon, C. Wong","doi":"10.1109/ECTC.2006.1645811","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645811","url":null,"abstract":"Recently, non-conductive adhesive (NCA) bonding technology has attracted increasingly research interests as lead-free interconnect due to the fine pitch capability and low cost. The NCA usually requires no conductive tillers, but needs a relatively high pressure for bonding between the IC chip and the substrate coupled with heat. During bonding, the heat and pressure are applied for some time and the direct physical contact between the two surfaces of the IC bump and the substrate bond pad can be made with NCA resin curing/solidification. Contact of bottom and top pads/electrodes, via their up-and-hill (represents the uneven bond pads surfaces) surface structures, leads to the electrical conduction of NCA joints. In order to create the electrically conductive NCA joints, relatively high pressure and high degrees of the solidification of the polymer resin are required. This paper introduces a novel lead-free nanoscale NCA interconnect material with trace amount of in-situ formed nanoconductive fillers. These uniformly distributed nanosized conductive fillers were in-situ formed in the epoxy resin and were well dispersed within the polymeric matrix. As such, the novel NCA joints were formed with lower bonding pressures and exhibited an improved electrical performance without sacrificing the fine pitch advantages of NCAs. The dramatic improvement was attributed to the enhanced interface properties by the nanoconductive fillers, which assisted the electrons tunneling and current flow","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling board-level four-point bend fatigue and impact drop tests","authors":"Chea Fx, J. Pang","doi":"10.1109/ECTC.2006.1645684","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645684","url":null,"abstract":"In this paper, modeling and simulation of board-level four-point bend fatigue and impact tests were investigated for 7 mm times 7 mm VQFN (48 I/O) assembly and 15 mm times 15 mm FBGA (324 I/O) assembly with Sn-Ag-Cu lead-free solder and OSP board surface finish. For cyclic bending fatigue, four-point bend cyclic loading at room temperature (25degC) and at high temperature (125degC) were investigated in order to develop bend fatigue model for Pb-free solder. The acceleration factor of failure at high temperature (125degC) to room temperature (25degC) is presented. Test results show that the cycle to failure increases significantly when bending displacement ranges decrease for both bend tests at 25degC and 125degC. The acceleration factor of cycle to failure due to high temperature (125degC) effect is higher than that due to room temperature effect. The FBGA component has higher bending fatigue resistance compared to VQFN component. Accumulated energy density per cycle at 125degC is more than that at 25degC significantly, which indicates that higher temperature accelerates bending fatigue failure of solder. Energy-based bending fatigue models were developed for Sn-Ag-Cu lead free solder subjected to cyclic bending load at 25degC and 125degC based on FEA result and experimental data. Using the same FEA model the loading was changed to simulate a four-point bend impact test with the same corresponding magnitude of bending curvatures. Comparisons of solder joint deformation response between the slow cyclic bend test and impact drop bend test are presented","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117227945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra thin hermetic wafer level, chip scale package","authors":"L. Shiv, M. Heschel, H. Korth, S. Weichel, R. Hauffe, A. Kilian, B. Semak, M. Houlberg, P. Egginton, A. Hase, J. Kuhmann","doi":"10.1109/ECTC.2006.1645794","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645794","url":null,"abstract":"This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121049232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Behavior of surface oxide and intermetallic compounds in interconnections of micro Sn-Ag solder bumps","authors":"T. Suga, H. Ozaki, H. Ozawa","doi":"10.1109/ECTC.2006.1645797","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645797","url":null,"abstract":"A flip-chip technology was put into practical use by interconnecting a chip-on-chip (CoC) with several thousands of micro-solder bumps with a diameter of 30 mum. Using this technology, the signal transmission rate between chips became comparable to system on chip (SOC) technology. This success with interconnects owes much to the characterization and control of the surface oxidation behavior of solder bumps and the growth of intermetallic compounds (IMCs), which influences the yield and reliability of solder bump interconnections. We clarified the growth behavior of solder oxide film and IMCs at the bonded interface of Sn 3.5 wt.% Ag solder bumps on Ni electrodes in the present research. As a result, we found an oxide film of solder with an initial thickness of 3 to 4 nm saturated at around 5 nm demonstrating an excellent solder interconnect. Although the interface between the solder and Sn-Ni IMCs roughens as they grow, the smoothness can be recovered by annealing at 100degC for 100 hr, resulting in a decrease in the fraction of the defect failure mode from 6% to about 0 to 3%","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Selective nickel and gold plating for enhanced wire bonding technology","authors":"T. Cheng, K. Petrarca, K. Srivastava, S. Knickerbocker, R. Volant, W. Sauter, S. McKnight, S. Allard, F. Beaulieu, D. Restaino, T. Hisada","doi":"10.1109/ECTC.2006.1645922","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645922","url":null,"abstract":"Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}