56th Electronic Components and Technology Conference 2006最新文献

{"title":"Demonstration of bidirectional optical link on optical PCB using a driver-receiver combined CMOS transceiver","authors":"Sae-Kyoung Kang, Tae-Woo Lee, S. Hwang, M. Cho, Hyo-Hoon Park","doi":"10.1109/ECTC.2006.1645867","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645867","url":null,"abstract":"For bidirectional optical link at 2.5 Gb/s, we designed and fabricated a driver-receiver combined CMOS transceiver in 0.18-mum technology, an optical connector, and an optical PCB. The CMOS transceiver provides both transmitting and receiving modes of operation on a single chip, showing -3-dB bandwidths of 2.2 GHz and 2.4 GHz, and small-signal isolations of -28 dB and -40 dB between operating modes, respectively. The optical PCB (OPCB) was fabricated as a multi-layered OPCB in which 2times6 channels fibers were embedded. The optical connector was designed as a 90deg-bent fiber connector which was fabricated by bending 2 times 12 multimode fibers and the bending radius of the fiber was 3.5 mm","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"20 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and thermal fatigue life of BGAs with eutectic Sn-Ag-Cu balls assembled at 210/spl deg/C with eutectic Sn-Pb solder paste","authors":"N. Nandagopal, Z. Mei, S. Teng","doi":"10.1109/ECTC.2006.1645759","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645759","url":null,"abstract":"Conventionally, it has been understood that in order to assemble BGAs with eutectic Sn-Ag-Cu solder balls in eutectic Sn-Pb solder paste, a reflow profile having a peak temperature higher than 217degC, which is the melting point of eutectic Sn-Ag-Cu, would be required to achieve complete mixing of the Sn-Pb paste and the Sn-Ag-Cu ball. Nevertheless, it was observed in this study that solder joints with uniform microstructure may be achieved with a peak reflow temperature of about 210degC. For further understanding of this phenomenon, DSC testing was performed on eutectic Sn-Ag-Cu spheres (of 0.406-0.76 mm diameters) placed over eutectic Sn-Pb solder paste of different volumes. It has been observed that the mixing of the Sn-Pb and Sn-Ag-Cu was accomplished in about 15 to 25 sees at a peak temperature of 210degC. Thermodynamic calculations published in the literature indicate that the liquidus temperature of completely mixed Sn-Pb and Sn-Ag-Cu is above 210degC. However, above 205degC the volume ratio of solid phase to liquid phase is very small, or practically negligible. The metallograph of Sn-Pb/Sn-Ag-Cu solder joints reflowed at 210degC peak temperature shows uniform microstructure. However, the distribution of Pb-rich phase inside the alpha Sn for the 210degC reflowed Sn-Pb/Sn-Ag-Cu solder joints was somewhat different from those of the 240degC reflowed Sn-Pb/Sn-Ag-Cu solder joints. Accelerated thermal cycling tests (0-100degC and -40-125degC) have been conducted on CSPs with eutectic Sn-Ag-Cu balls assembled on PCBs (of 0.093\" and 0.125\" thick) with eutectic Sn-Pb solder paste. SnPb and Pb-free control samples were also included. These parts were assembled in both single and double-sided board configurations and were reflowed with peak temperatures of 210degC and 227deg C. The ATC test results showed that the fatigue life of CSP assemblies reflowed at 210deg C and 227degC had no significant difference","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effect of co-planarity variation on anisotropic conductive adhesive assemblies","authors":"G. Dou, D. Whalley, Changqing Liu","doi":"10.1109/ECTC.2006.1645766","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645766","url":null,"abstract":"Anisotropic conductive adhesives (ACAs) consist of a polymer adhesive matrix containing fine conductive particles dispersed either randomly, or more rarely in an ordered way. The primary objective of this experimental research was to understand the effects of a non-uniform bond thickness due to non co-planarity of the component or substrate terminations in ACA assemblies. This has been achieved through measurements of the conductivity variations of ACA joints in a number of ACA assemblies, where the component bump plane and substrate plane were deliberately held in different degrees of relative rotation from parallel during adhesive cure. Measurements of the joint resistances versus rotational angle, for a constant bonding force, were made for 10 levels of rotation of the chips relative to the substrates. The results showed that the resistances of the joints in the assemblies exhibited three distinct types of behaviour: stable joint resistances; gradually increasing resistances and unstable resistances. In conclusion, it is shown that ACA joints are very sensitive to the uniformity of the bond thickness, as the larger the rotations were, the lower and less uniform the joint conductivities were, however, the joints were uniform if the rotation angles were controlled within certain limits","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115064867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stacked die SiP technology suitable for devices with low-k inter-layer dielectric","authors":"Y. Matsuura, A. Watanabe, S. Kawakami","doi":"10.1109/ECTC.2006.1645837","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645837","url":null,"abstract":"This paper presents the stacked die SiP technology suitable for the devices with low-k inter-layer dielectric \"low-k ILD\". As devices with low-k ILD increase in number, they have also come to be used in stacked die SiP. The low-k ILD material is however, known to have a fragile characteristic. Combined with the stacked die SiP which has a limitation in die size and height for use in cellular phones and the like, it is very important to care about the influence on the device with low-k ILD because package structure is complex and the die thickness needs to be thin. To develop this type of stacked die SiP, we investigated and focused on two subjects. One was, how to control the thermal and mechanical stress on the die in the assembly. The other was, how eliminate cracks in the low-k ILD. On the first subject, the suitable package structure was examined to minimize the stress on the device with low-k ILD, and the result was that the structure of the device with low-k ILD placed the top of the stacked dies is the best. However, this has an overhang on the device with low-k ILD. There is therefore a risk of damaging the device with low-k ILD as the die is stressed during the wire bonding process. We therefore examined wire bonding conditions with simulation of stress by the bonding load on the die in advance, and from there, established the suitable wire bonding process. On the second subject, the dicing process exposes the die to the generation of crack initiation points. After the evaluation, the new dicing process with the laser groove dicing was effective in controlling possibilities of crack occurrence in devices experiencing large stress. Thus, this new process is applied to the product depending on a package structure, a package type, and so on. Finally, samples of real products in mass production were put through reliability tests and they passed. Stacked die SiP for thin devices with low-k ILD technology has therefore been established","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115246351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing geometrical design of superhydrophobic surfaces for prevention of microelectromechanical system (MEMS) stiction","authors":"Lingbo Zhu, Y. Xiu, Jianwen Xu, D. Hess, C. Wong","doi":"10.1109/ECTC.2006.1645795","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645795","url":null,"abstract":"Due to the surface smoothness of micromachined structures, strong adhesion forces between these fabricated structures and the substrate can be developed. The major adhesion mechanisms include capillary forces, hydrogen bonding, electrostatic forces and van der Waals forces. Once contact is made, the magnitude of these forces is in some cases sufficient to deform and pin these structures to the substrate, resulting in device failure. This type of failure is one of the dominant sources of yield loss in MEMS. The basic approaches to prevent stiction are increasing surface roughness and/or lowering solid surface energy by coating with low surface energy materials. Combination of micro- and nano-meter scale roughness can dramatically increase the surface roughness. However, in fabrication process, how to optimally design surface geometry with micro-/nano-meter roughness is still not clear. The objectives of this paper are to experimentally study the wetting and hydrophobicity of water droplets on two-tier rough surfaces for comparison with theoretical analyses, and to optimize the surface geometrical design for fabricating stable superhydrophobic surfaces. Two model systems are fabricated: carbon nanotube arrays on silicon wafers and carbon nanotube arrays on carbon nanotube films, to compare wetting on micro-patterned silicon surfaces with wetting on nano-scale roughness surfaces. All surfaces are coated with 20 nm thick fluorocarbon films to obtain low surface energies and to improve the stability of the superhydrophobic surface, formed by plasma enhanced chemical vapor deposition (PECVD). The results show that the microstructural characteristics must be optimized to achieve stable superhydrophobicity on micro-scale rough surfaces. However, the presence of nano-scale roughness allows a much broader range of surface design criteria, decreases the contact angle hysteresis to less than 1deg and establishes stable and robust superhydrophobicity, although nano-scale roughness could not increase the apparent contact angle significantly if the micro-scale roughness dominates. The results of the research could guide the optimized designs of the surfaces for prevention of microelectromechanical (MEMS) stiction","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116060072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low electrical resistance silicon through vias: technology and characterization","authors":"D. Henry, D. Belhachemi, J. Souriau, C. Brunet-Manquat, C. Puget, G. Ponthenier, J. L. Vallejo, C. Lecouvey, N. Sillon","doi":"10.1109/ECTC.2006.1645834","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645834","url":null,"abstract":"System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures, which combine disparate technologies. In particular, when several die have to be connected in a small package, stacking would appear to be the best solution. However, this 3D packaging approach has to satisfy the constraints of high interconnection density and high data throughput in conjunction with good signal integrity, and reliability while maintaining a low cost. Today, several different approaches have been developed in order to perform 3D packaging. These include technologies like SiP (system in package), SoC (system on chip) or SoP (system on package) based in R. R. Tummala et al. (2002). A concept for heterogeneous integration has been developed by CEA-LETI and is called SoW (system on wafer) as presented in N. Sillon et al. (2005). In this paper, the system on wafer concept (SoW) is presented. In order to perform heterogeneous integration by using the SoW, a technological toolbox is required. This toolbox is presented with a focus on the silicon through vias technology (STV). Then, the complete technology for the STV is presented. A specific study concerning insulation conformity into the silicon through vias has been led and the results that are presented. Finally, electrical tests results are shown for different vias geometries","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122498655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effective thermal via and decoupling capacitor insertion for 3D system-on-package","authors":"E. Wong, J. Minz, S. Lim","doi":"10.1109/ECTC.2006.1645903","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645903","url":null,"abstract":"The increased component density of a 3D system-on-package (SOP) exacerbates the thermal hotspot problem. A popular choice to mitigate the thermal issues is thermal vias (t-vias) that are used to establish thermal paths from the core of an SOP package to the heat sinks. Another major problem with SOP integration is the power supply noise coupling among various mixed signal components constituting the system. In this case, decoupling capacitors (decaps) are inserted to provide the switching currents locally. The goal of our automatic 3D SOP component placement algorithm is to determine the x/y/z location of each component while minimizing the footprint area under thermal and power supply noise constraints. In general, t-vias and decaps are typically inserted in the white space in the placement, whereas the proximity of the t-vias and decaps to the target components determines their effectiveness. Hence, our component placer considers t-via and decap insertion during the early design stage, where the component location can be flexibly changed. Related experiments demonstrate the effectiveness of our approach","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114400949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of finite element modeling techniques on solder joint fatigue life prediction of flip-chip BGA packages","authors":"Xuejun Fan, M. Pei, P. Bhatti","doi":"10.1109/ECTC.2006.1645772","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645772","url":null,"abstract":"Solder joint fatigue life in thermal cycling has been studied for decades using the finite element method. A great variety of modeling methodologies such as global/local modeling (sub-modeling) and sub-structure modeling (superelement) has been developed. Many different types of constitutive equations for solder alloys, various loading assumptions, and several definitions of damage parameters have been used. However, the accuracy of these different modeling approaches has not been completely evaluated in literature. There has been some long-standing confusion regarding the modeling assumptions and their effect on the accuracy of models, such as the initial stress-free temperature setting, selection of damage parameters, and choice of element type. This paper presents a comprehensive study of finite element modeling techniques for solder joint fatigue life prediction. Several guidelines are recommended to obtain consistent and accurate finite element results","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128252200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of 3D stack package using silicon interposer for high power application","authors":"N. Khan, S. Yoon, A. Viswanath, V. Ganesh, D.W. Ranganathan, S. Lim, K. Vaidyanathan","doi":"10.1109/ECTC.2006.1645742","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645742","url":null,"abstract":"Stacking of many functional chips in a 3D stack package leads to high heat dissipation. Therefore a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3D stacked package with silicon interposers is developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer are formed by through silicon via. Silicon has much high thermal conductivity than organic interposers, which reduces drastically the package thermal resistance. Thermal performances of the 3D package are analyzed and thermal enhancement methods like thermal vias, thermal bridging are evaluated. The designed package is having 5 times lesser thermal resistance compared to the package with organic substrate. An additional silicon heat spreader is attached to the package for high power application. Numerical analysis and experimental validation are carried out. The designed 3D stack package is found suitable for 20 watts heat dissipation","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128345730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on bubble formation in rigid-flexible substrates bonding using anisotropic conductive films (ACFs) and their effects on the ACF joint reliability","authors":"H. Kim, C. Chung, M. Yim, Soon-Min Hong, S. Jang, Young-Joon Moon, K. Paik","doi":"10.1109/ECTC.2006.1645769","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645769","url":null,"abstract":"Because of downsizing of electronic products and cost effectiveness, rigid substrate-flexible substrate (RS-FS) bonding technology using ACFs becomes more important as an alternative to socket type connectors and rigid/flex substrates. However, formation of process related bubbles, entrapped inside the ACF layer during bonding processes, is strongly influenced by process variables, such as a bonding pressure and a bonding temperature. These bubbles can reduce adhesion strength of ACFs joints, and induce moisture penetration path and entrapment location during reliability tests in humid environments. However, the causes of bubbles formation during the ACF bonding process and the effect of bubbles on ACFs joints reliability have not been fully understood. Bonding process variables, such as bonding temperature, bonding pressure and flexible substrate (FS) types, were changed in order to investigate their effects on bubbles formation. According to the results, the tendency of bubbles formation was closely related to these three factors. The bubble area increased as the bonding temperature increased. Moreover, same tendency was observed against the bonding pressure changes at fixed bonding temperature conditions. Two different FSs, which have different surface roughness and energies, were used and the bubbles formed only at the FS with larger roughness and lower surface energy. According to the results from surface energy measurement of FSs by using goniometry, the FS with higher surface energy is favorable for bubble free assembly because higher surface energy provides better wettability. Therefore, Ar and O2 plasma treatments were performed on the FS with lower surface energy to improve the wettability, and bubbles were significantly removed. Finally, two types of test vehicles (TVs), without (type 1) and with bubbles (type 2), were assembled to investigate the effects of bubbles on the ACFs joints reliability in humid environments, such as PCT (pressure cooker test). All type 2 TVs, with bubbles, were electrically failed after 72 hours of PCT because the process related bubbles acted as a moisture penetration path and entrapment sites. However, all type 1 TVs survived even after 120 hours of PCT","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}