56th Electronic Components and Technology Conference 2006最新文献

{"title":"Mixed mode bending test for interfacial adhesion in semiconductor applications","authors":"J. Thijsse, W. V. van Driel, M. van Gils, O. van der Sluis","doi":"10.1109/ECTC.2006.1645917","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645917","url":null,"abstract":"Currently, prediction of interface strength is typically done using the critical energy release rate. Interface strength, however, is heavily dependent on mode mixity. Accurately predicting delamination therefore requires a material model that includes the mode dependency of interface strength. A novel test setup is designed which allows mixed mode delamination testing. The setup is a stabilized version of the mixed mode bending test previously described by Reeder and Crews (1990; 1991). It allows for the measurement of stable crack growth over the full range of mode mixities, using a single specimen design. The crack length, necessary for calculation of the energy release rate, is obtained from an analytical model. Crack length and displacement data are used in a finite element model containing a crack tip to calculate the mode mixity","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130652280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-chip integration on a PLC platform for 16 /spl times/ 16 port optical switch using passive alignment technique","authors":"J. Lim, Hwe-Jong Kim, Seon Hoon Kim, B. Rho","doi":"10.1109/ECTC.2006.1645896","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645896","url":null,"abstract":"We propose simple assembly techniques capable of performing high density multi-chip integration on a PLC platform with eutectic AuSn solder bumps, for 16x16 port SOA gate switch composed 2 times 2 optical switch SOA array chips using passive alignment technique. Conventional methods have used chip-by-chip bonding method. These methods are found it is difficult to obtain high bonding strength because the solder interconnections remelt during repeated bonding steps. To overcome this problem, we investigated the single re-flow processes and optimized the bonding condition for non re-flow process on minimum AuSn solder bump spreading. Also, die shear tests were conducted to evaluate mechanical reliability between the solder bump and the chip pads","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114801318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparative study of the failure mechanisms encountered in drop and large amplitude vibration tests","authors":"P. Marjamaki, T. Mattila, J. Kivilahti","doi":"10.1109/ECTC.2006.1645631","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645631","url":null,"abstract":"Drop tests are commonly used to study the reliability of components under shock loading conditions. However, to overcome some of the drawbacks inherent to drop testing systems, the applicability of large amplitude vibration test to reliability assessment has been investigated by comparing the vibration behaviors and failure modes of component boards in the two tests. The component boards and the drop test parameters are in accordance with the JESD22-B111 standard and the parameters of the vibration test are adjusted to produce equivalent loading. The drop and vibration tests were compared by evaluating first the loading conditions with the finite-element method as well as experimentally. The results show that by applying the harmonic vibration loadings to component boards at their natural resonance frequencies very similar loading to drop testing can be achieved even though there are some differences in the bending behavior of the boards during testing. The vibration amplitude was found to be the key parameter determining the type of failure mode in the vibration test. The failure modes in the vibration test were found to be the same as those in the drop test: failure of the reaction layers on the component and board side of the solder interconnections and failure of the resin coated copper layers of the printed wiring boards. In addition, failures of copper traces were observed in vibration tested assemblies. The cracking of the bulk solder was observed with small vibration amplitudes (2.3 mm), but the failure mode changed to intermetallic cracking -as in drop testing - once the vibration amplitude was increased to 4.7 mm. According to the results of this study the vibration test can be employed in studying failure modes and mechanisms under shock loading conditions","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124493091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal stress analysis of a flip-chip parallel VCSEL (vertical-cavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints","authors":"J. Lau, W. Dauksher","doi":"10.1109/ECTC.2006.1645777","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645777","url":null,"abstract":"Solders such as the 48wt%Sn-52wt%In, 42wt%Sn-58wt%Bi, 63wt%Sn-37wt%Pb, Sn(3-4)wt%Ag(0.5-0.7)wt%Cu, and 80wt%Au-20wt%Sn, are studied as interconnect materials in a vertical-cavity surface-emitting laser (VCSEL). The Sn52In alloy is a low temperature (melting point = 118degC) lead-free solder and a potential candidate material for this device. In this study, thermal-structural analysis evaluates the solder alloys in the context of in-service operating conditions. Specifically, the thermal analysis determines the in-service temperature distributions, as influenced by each solder alloy, due to power generation within the VCSEL and due to convective boundary conditions. Subsequently, these thermal profiles are used as the thermal loads in an evaluation of the stress and creep response in the laser pads and solder joints. Emphasis is placed on the relaxation of stresses at the laser pads and on the creep strains developed at the solder joints during a 24 hour power-on condition","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design & development of a large die and fine pitch wafer level package for mobile applications","authors":"V. Kripesh, Xiaowu Zhang, N. Khan, M. Rotaru, C. T. Chong","doi":"10.1109/ECTC.2006.1645706","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645706","url":null,"abstract":"Wafer level packaging offers the advantage of chip scale packaging with an efficient production approach. In addition to size, cost and ease of logistics make it as a main stream packaging solution for a single chip. Resulting saving in size, cost has also resulted in limitation of using conventional wafer level packaging for large die size and high IO devices. This paper reports the development of a wafer level package with 440 IOs, 400 microns pitch and 12times12 mm die size for mobile applications. The package format and IOs are distributed in such way to achieve a clock frequency of 4.8 GHz for digital applications. Package thermal performance has been optimized by incorporating thermal vias and thermal balls. The paper also reports the development of a thin heat pipe with plate pin heat sink and optimization results to meet a 5W power dissipation. Package thermal resistance and cooling solution thermal performance have been measured and correlated with the simulation models. The structural modeling simulated the thermo-mechanical stresses in the package and predicted its characteristic life. The simulated results matched well with the reliability results. The paper also reports the reliability results of the package and especially the performance of the package under drop testing which is critical for mobile applications","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wavelength matching and tuning in green laser packaging using second harmonic generation","authors":"Xingsheng Liu, M. Hu, L. Hughes, C. Zah","doi":"10.1109/ECTC.2006.1645785","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645785","url":null,"abstract":"Short wavelength laser sources, such as green laser sources, have found increased applications. Laser wavelengths, such as green light, which cannot be generated by a single native semiconductor laser source, can be obtained using the nonlinear susceptibility of many optical materials. For green laser sources capable of high speed modulation, the combination of a quasi-phase-matched second harmonic generation (SHG) waveguide device and a single-wavelength distributed-Bragg-reflector (DBR) laser diode is promising. The wavelength conversion efficiency of a SHG is strongly dependent on the wavelength matching between the DBR laser diode and the SHG device, posing a significant challenge in green laser packaging. It is desired that the wavelength matching is achieved at high efficiency and thus low power consumption. In this paper, the wavelength matching between a DBR laser diode and a SHG device is discussed and thermal wavelength tuning of both laser and SHG device is designed and studied","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132323562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High capacitance, large area, thin film, nanocomposite based embedded capacitors","authors":"R. Das, M. Poliks, J. Lauffer, V. Markovich","doi":"10.1109/ECTC.2006.1645856","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645856","url":null,"abstract":"This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives, their integration in PWB substrates and the reliability of the embedded capacitors. A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. Nanocomposites resulted in high capacitance density (10-100 nF/inch2) and low loss (0.02-0.04) at 1 MHz. The manufacturability of these films and their reliability has been tested using large area (13 inch times 18 inch or 19.5 inch times24 inch) test vehicles. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (pressure cooker test) and solder shock. Capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 degC) and 1400 cycles DTC (deep thermal cycle)","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ensuring passivity and automatic order selection for global rational approximation macromodeling","authors":"A. Hillegonds, K. Melde, J. Prince","doi":"10.1109/ECTC.2006.1645884","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645884","url":null,"abstract":"Today digital and wireless designs demand both increasingly higher frequencies and better performance. As overall model complexity grows, greater importance is placed on the development of accurate, efficient interconnect simulation tools. One common approach is to use frequency domain macromodels of the network. This paper concentrates on the global rational approximation macromodeling technique as in the method developed by Elzinga (Elzinga, 2000). Here the technique is improved upon by enforcing passivity for macromodels where only minor passivity violations occur. In addition, an improved automated order selection method for the rational polynomial was developed and applied to the specific program of (Elzinga, 2000) to test the method","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130249088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MCM LGA package with optical I/O passively aligned to dual layer polymer waveguides in PCB","authors":"F. Libsch, R. Budd, P. Chiniwalla, P. Hobbs, M. Mastro, J. Sanford, J. Xu","doi":"10.1109/ECTC.2006.1645886","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645886","url":null,"abstract":"Over the past 30 years, IBM has provided leadership in high density I/O density and count interconnects at both chip and package levels as has been necessary for processor chips in high end symmetrical multiple processor (SMP) servers. For example, IBM introduced multi-chip modules (MCMs) in the 1970's, thermal conduction modules (TCMs) in the 1980's, and advanced organic micro-via buildup-layer packages in the 1990's (Patel, 2005). Typically, MCMs are necessary to provide significant increases in bandwidth between chips on the module, compared to the alternative route of lower bandwidth resulting from chip-to-chip interconnects going through the printed circuit board (PCB) for single chip modules (SCMs). CMOS chip-to-package pad scaling gap has been growing compared to the package-to-printed circuit board (PCB) pad scaling, which is the reason for the I/O advantage of MCMs vs. SCMs. For example, today's mainstream IC-to-package flipchip bonding uses 0.1 mm square pads on 0.2 mm pitch, with 0.15 mm ramping up, while the package-to-PCB ball- or land grid array (BGA or LGA) pitch uses 1-mm pitch, an areal density as much as 64 times lower. However, even with the larger bandwidth advantage of MCMs, more complex chips such as multiprocessor cores and the need for higher bandwidth to memory cache require a relatively larger number of signal I/Os, as well as more power and ground I/Os. Faster I/O clocks further exacerbate the need for more package I/O by forcing the transition from previous single-ended I/Os to differential signal I/Os to satisfy the higher frequency bit error rate specifications on SMP buses. Our goal is to alleviate the I/O bottleneck at the packaging level in the most cost effective manner, while providing the lowest risk, most flexible development package. To this end, we present our work on an electrical LGA field replaceable package with optical components. These optical components enable larger I/O bandwidth density between the MCM and PCB than that allowed by a standard electrical package","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134146052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect detection of flip chip solder bump with wavelet analysis of laser ultrasound signals","authors":"Jin Yang, Lizheng Zhang, I. C. Ume","doi":"10.1109/ECTC.2006.1645713","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645713","url":null,"abstract":"A novel laser ultrasound and interferometer inspection system has been successfully applied to detect interconnection defects including missing, misaligned, open, and cracked solder bumps in flip chips, chip scale packages and chip capacitors. In this paper, wavelet analysis of ultrasound vibration signals is presented and compared to previous methods, including error ratio and correlation coefficient. Wavelet analysis increases the sensitivity to defect detection of flip chip solder bumps. The versatility of the system for inspecting flip chips solder joints made from eutectic and lead-free materials is discussed. The results show that wavelet analysis is a strong tool for ultrasound vibration signal processing. Wavelet analysis has the capability for real-time processing and can improve the efficiency of on-line evaluation. The fully developed system can be used online and serve as a real-time inspection tool for solder bump interconnections in the manufacturing process of electronic packages. It can be concluded that the developed system is capable for quality inspection of solder bumps made from tin-lead and lead-free materials","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134520870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}