Multi-chip integration on a PLC platform for 16 /spl times/ 16 port optical switch using passive alignment technique

Abstract

We propose simple assembly techniques capable of performing high density multi-chip integration on a PLC platform with eutectic AuSn solder bumps, for 16x16 port SOA gate switch composed 2 times 2 optical switch SOA array chips using passive alignment technique. Conventional methods have used chip-by-chip bonding method. These methods are found it is difficult to obtain high bonding strength because the solder interconnections remelt during repeated bonding steps. To overcome this problem, we investigated the single re-flow processes and optimized the bonding condition for non re-flow process on minimum AuSn solder bump spreading. Also, die shear tests were conducted to evaluate mechanical reliability between the solder bump and the chip pads