Development of 3D stack package using silicon interposer for high power application

Abstract

Stacking of many functional chips in a 3D stack package leads to high heat dissipation. Therefore a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3D stacked package with silicon interposers is developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer are formed by through silicon via. Silicon has much high thermal conductivity than organic interposers, which reduces drastically the package thermal resistance. Thermal performances of the 3D package are analyzed and thermal enhancement methods like thermal vias, thermal bridging are evaluated. The designed package is having 5 times lesser thermal resistance compared to the package with organic substrate. An additional silicon heat spreader is attached to the package for high power application. Numerical analysis and experimental validation are carried out. The designed 3D stack package is found suitable for 20 watts heat dissipation